Packaging structure and packaging method of fingerprint recognition chip

A fingerprint recognition and packaging structure technology, applied in character and pattern recognition, acquisition/organization of fingerprints/palmprints, instruments, etc., can solve the problems of low yield and large thickness of fingerprint recognition package, achieve high yield and improve process Stability and applicable range, the effect of broad application prospects

Active Publication Date: 2017-09-08
SJ SEMICON JIANGYIN CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging structure and packaging method for fingerprint identification chips, which are used to solve the problems of relatively large thickness and low yield of fingerprint identification chips in the prior art.

Method used

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  • Packaging structure and packaging method of fingerprint recognition chip
  • Packaging structure and packaging method of fingerprint recognition chip
  • Packaging structure and packaging method of fingerprint recognition chip

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Embodiment Construction

[0061] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] see Figure 3 ~ Figure 12 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the...

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Abstract

The invention provides a packaging structure and a packaging method of a fingerprint recognition chip. The packaging structure comprises a silicon substrate, a re-wiring layer formed on the silicon substrate, metal leading wires welded on the re-wiring layer through a wire-welding process, the fingerprint recognition chip arranged above the re-wiring layer through metal welding points, and a packaging material covering the fingerprint recognition chip, wherein the front surface of the fingerprint recognition chip is arranged towards the re-wiring layer, and the metal leading wires are exposed out of the packaging material. According to the packaging structure and the packaging method, the fingerprint recognition chip is packaged in a fan-out manner, compared with conventional packaging of other fingerprint recognition chips, the cost is low, the thickness is small, and the yield is high; and by employing the wire-welding process, the process temperature can be greatly reduced, and the application range of the process is extended.

Description

technical field [0001] The invention relates to a semiconductor package structure and a package method, in particular to a package structure and a package method of a fingerprint identification chip. Background technique [0002] With the increasingly powerful functions of integrated circuits, higher performance and higher integration, and the emergence of new integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and in the value of the entire electronic system The proportion is increasing. At the same time, as the feature size of integrated circuits reaches the nanometer level, transistors are developing towards higher density and higher clock frequency, and packaging is also developing towards higher density. [0003] Due to the advantages of miniaturization, low cost and high integration, as well as better performance and higher energy efficiency, fan-out wafer-level packaging (fowlp) technology has become a An im...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/492H01L23/498H01L21/56H01L21/60G06K9/00
CPCH01L23/49816H01L24/81H01L24/83H01L21/56H01L23/3171H01L23/4924H01L2224/83491G06V40/12
Inventor 陈彦亨林正忠何志宏林政达
Owner SJ SEMICON JIANGYIN CORP
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