A Two-Stage Switch Structure Implementation Method Based on Adjacent Port Scheduling Information

Abstract

The invention discloses a two-stage switching structure realization method based on adjacent port scheduling information, including two-stage crossbar, input buffer and intermediate buffer; data communication links are set between adjacent input ports, and before the end of each time slot, each The input port copies the scheduling result information of this time slot to the adjacent input port through the communication link, and the intermediate port transmits the cached information to the output port through the second-level crossbar, and the output port feeds it back to the input of the same line card Port: The input port of each time slot performs algorithm scheduling according to the above two types of information received and the local buffer information at the moment, and selects the cell to be forwarded to the intermediate port in the next time slot. The invention expands the time domain space of the scheduling algorithm, and can support larger-scale switching modules and higher switching rates; using the scheduling result information of adjacent ports and the feedback information of intermediate ports, the input port can predict the target port of the next time slot in advance The accurate information of the cache queue avoids the cell conflict problem.

Description

technical field [0001] The invention relates to the technical field of Internet information transmission, in particular to a method for realizing a two-stage switching structure based on adjacent port scheduling information. Background technique [0002] The development of optical communication technologies such as dense wavelength division multiplexing has enabled the data transmission rate of optical fibers to reach 400Gbps, but the switching rate of network transmission equipment (such as switches and routers) is far lower than the data transmission rate in the optical domain, which makes network transmission equipment Become the bottleneck of Internet performance. The key factors that affect the data transmission rate of network equipment are the switching structure adopted by the core switching chip and the corresponding cell forwarding scheduling algorithm. Therefore, the high-performance switching structure and the scheduling algorithm that work with it become the cor...

AI Technical Summary

Problems solved by technology

[0009] (2) The time limit of FMLB on the scheduling algorithm

Although the feedback process of N-bit cache information takes less time because the input and output ports are located on the same line card, for an algorithm that requires N times of searching and multiple comparison operations in the worst case, the crossbar reconfiguration time Complete Feedback and Scheduling is not achievable

[0013] From the above analysis, it can be seen that although FMLB shows excellent switching performance in the simulation, the serial working mode of the cell transmission and scheduling algorithm in this structure requires the scheduling algorithm to be completed in a very short time. In the worst case, it is necessary to search For an algorithm that needs N times and multiple comparison operations, it is impossible to complete the feedback and scheduling within the crossbar reconfiguration time. This time limit will inevitably lead to the time-consuming scheduling algorithm far exceeding the crossbar reconfiguration time, and cell transmission cannot be achieved. Without waiting for the scheduling result, the time slot length will inevitably increase due to the scheduling algorithm, which will limit the increase of the port rate and reduce the high-speed switching capability and scalability of FMLB

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