Chip stack three-dimensional packaging structure

Abstract

The invention discloses a chip stack three-dimensional packaging structure which includes a memory chip stack body, a rewiring layer, a substrate, and a cache chip. A mounting surface of the memory chip stack body includes a flip-chip bonding area. The rewiring layer is formed on the mounting surface of the memory chip stack body. The substrate has a window hole, and the mounting surface of the memory chip stack body is mounted under the substrate so that the flip-chip bonding area of the memory chip stack body can be completely exposed in the window hole of the substrate. The cache chip is arranged on the flip-chip bonding area of the memory chip stack body via the window hole in an aligned manner, and is bonded to the rewiring layer in a flip-chip manner. The substrate and the cache chip are distributed on one side of the rewiring layer, while the memory chip stack body is arranged on the other side of the rewiring layer. Through the rewiring layer, the substrate and the cache chip are connected, and the cache chip and the memory chip stack body are connected. The thickness and size of the packaging structure are reduced, and the signal transmission path is shortened.

Description

technical field [0001] The invention belongs to the field of packaging of semiconductor storage devices, and in particular relates to a three-dimensional packaging structure of chip stacks. Background technique [0002] Ball Grid Array (BGA) packaging technology is a surface mount technology applied to integrated circuits. Ball contacts are made in an array on the back of the substrate as pins, and large-scale integrated circuits are assembled on the front of the substrate. , is a surface mount packaging technology commonly used in multi-pin large-scale integrated circuits. [0003] At present, according to the different assembly methods of integrated circuits, the BGA packaging structure is divided into two types. The first is a parallel multi-chip ball grid array package structure, such as figure 1 As shown, ball grid array pins 105 are distributed on the back side of the substrate 100, and the cache chip 102 and the memory chip stack body 103 are connected to the front ...

AI Technical Summary

Problems solved by technology

Because in this packaging technology, the substrate 200, the memory chip stack body 203 and the cache chip 202 are all arranged symmetrically, it will not cause the flow imbalance in the injection molding process, but the signal transmission distance will be too long if connected by wires, and Since the substrate 200, the memory chip stack body 203 and the cache chip 202 are stacked, the thickness of the packaging structure is relatively large

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