A High-Bandwidth Multi-Scale Fault Bitmap Cache Structure

A fault-bit, high-bandwidth technology, applied in memory systems, instruments, electrical and digital data processing, etc., can solve problems such as abnormal cache operation and logical organizational structure failure, and achieve low latency overhead, fast query speed, and low storage overhead. Effect

Active Publication Date: 2018-07-03
BEIJING UNIV OF POSTS & TELECOMM
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Problems solved by technology

These bit failures will cause the failure of the logical organization structure of the cache at all levels, causing the cache to work abnormally

Method used

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  • A High-Bandwidth Multi-Scale Fault Bitmap Cache Structure
  • A High-Bandwidth Multi-Scale Fault Bitmap Cache Structure
  • A High-Bandwidth Multi-Scale Fault Bitmap Cache Structure

Examples

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Embodiment Construction

[0046] The following examples illustrate the access query methods of static allocation and dynamic allocation:

[0047] Static allocation:

[0048] An ordinary cache group with an association degree of 8 in the L1 cache, the number of cache groups is 4, the number of bytes in the cache line is 64 bytes, and the size of the sub-block is 8 bytes. Each cache group is assigned a fixed fault bitmap item for 3. The content of the initial cache group and cache line fault bitmap array, the content and physical address of the subblock fault bitmap array are as follows Figure 5shown. When a cache request R1 occurs, the physical address is 00000011000, and the first line is searched in the cache group and cache line fault bitmap array according to its index value 00. The fault bitmap field of the cache group is 01, indicating that the cache group is faulty. And the fault can be repaired, continue to access the cache line fault bitmap field, its value is 10011000. At the same time, a...

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Abstract

The invention provides a mechanism and storage structure capable of checking cache logic structure faults of all levels in a quick and high-bandwidth way. Buffer sets, buffer lines and fault conditions of buffer sub-blocks can be marked in a multiscale way; and a high-performance fault tolerance buffer structure can be supported. Two different bitmap spatial configuration ways including static distribution and dynamic distribution can be provided; and low storage expense can be achieved.

Description

Technical field [0001] The patent of the present invention relates to a fast and high-bandwidth mechanism and storage structure for marking the distribution of faults in the logic organization structure at all levels in the cache array. Background technique [0002] Not only the permanent faults caused by missed detection and wear and aging will affect the reliability of the chips after leaving the factory, but also the gaps that are difficult to detect before leaving the factory, occur randomly in time, have a fixed position, last for a certain period, but are recoverable Bit failure also has a serious impact on the reliability of the chip after leaving the factory. Efficient error correction for transient faults Error detection codes also face the problem of high delay overhead when dealing with intermittent bit failures, and will weaken the handling of transient faults, causing multi-bit faults. Effectively flagging these bit faults becomes a requirement for the cache to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0802
CPCG06F12/0802
Inventor 黄智濒刘欣王珏满柯宇许瀚元周锋桑燊
Owner BEIJING UNIV OF POSTS & TELECOMM
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