Read-decoupling storage unit based on FinFET device

A storage unit and device technology, applied in information storage, static storage, digital storage information, etc., can solve the problems of destroying the data value of the storage point, unstable storage results, and large delay.

Active Publication Date: 2017-11-21
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The storage unit may destroy the data value stored in the storage point during the read operation, and there is a serious problem of small noise tolerance of the read operation, which leads to unstable storage results and unstable circuit functions; moreover, it is composed of FINFET tube M3 and FINFET tube M4 The pull-down network of the storage unit has two leakage current paths when the storage unit is in the holding state, so the leakage current is large, resulting in large leakage power consumption and large delay, which is not conducive to fast and stable data access

Method used

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  • Read-decoupling storage unit based on FinFET device
  • Read-decoupling storage unit based on FinFET device
  • Read-decoupling storage unit based on FinFET device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0015] Embodiment one: if figure 2 As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decouplin...

Embodiment 2

[0016] Embodiment two: if figure 2 As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decouplin...

Embodiment 3

[0018] Embodiment three: as figure 2 As shown, a read decoupling memory unit based on a FinFET device includes a write word line WWL, a write bit line WBL, an inverted write bit line WBLb, a read word line RWL, a read bit line RBL, a first FinFET tube B1, a second FinFET B2, third FinFET B3, fourth FinFET B4, fifth FinFET B5, sixth FinFET B6, seventh FinFET B7, eighth FinFET B8, ninth FinFET B9, first FinFET B1, the second FinFET tube B2 and the seventh FinFET tube B7 are respectively low-threshold P-type FinFET tubes, the third FinFET tube B3, the fourth FinFET tube B4, the fifth FinFET tube B5, the sixth FinFET tube B6 and the ninth FinFET tube Tube B9 is an N-type FinFET tube with a low threshold, the eighth FinFET tube B8 is an N-type FinFET tube with a high threshold, the source of the first FinFET B1, the source of the second FinFET B2, and the seventh FinFET B7 The source of the read decoupling storage unit is connected to the power supply terminal of the read decoupl...

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PUM

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Abstract

The invention discloses a read-decoupling storage unit based on a FinFET device. The read-decoupling storage unit comprises a writing word line, a writing bit line, an antiphase writing bit line, a reading word line, a reading bit line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET, an eighth FinFET and a ninth FinFET, wherein the first FinFET, the second FinFET and the seventh FinFET are P-type FinFETs with low threshold values, the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the ninth FinFET are N-type FinFETs with low threshold values, and the eight FinFET is an N-type FinFET with a high threshold value. The read-decoupling storage unit has the advantages that under the condition of not influencing circuit performance, delay, power consumption and a power consumption delay product are all small, data values stored in memory points cannot be damaged during reading operation, and storage results and circuit functions are high in stability.

Description

technical field [0001] The invention relates to a storage unit, in particular to a read decoupling storage unit based on a FinFET device. Background technique [0002] As the process size enters the nanometer level, power consumption has become a problem that IC designers have to pay attention to. In most digital systems, memory power consumption accounts for an increasing proportion of total circuit power consumption. Static Random Access Memory (SRAM, Static Random Access Memory) is an important component in memory, so it is of great research significance to design SRAM with high stability and low power consumption. The SRAM is mainly composed of a storage array and other peripheral circuits, and the storage array is composed of a storage unit, which is the core of the SRAM, and the performance of the storage unit directly determines the performance of the SRAM. [0003] As the size of transistors continues to shrink, limited by the short-channel effect and the current m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/40
Inventor 胡建平杨会山
Owner NINGBO UNIV
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