Clock data recovery circuit and method

Abstract

The invention provides a clock data recovery circuit and method. The clock data recovery circuit comprises a data acquisition module, a signal quality detection module, a phase discrimination module and a delay chain, and is characterized in that the data acquisition module acquires data received by a high-speed serial interface receiving terminal and recovers the sampled data to full-swing data; the signal quality detection module stores the sample data, compares the sampled data with the full-swing data, labels signals which are inconsistent with the full-swing data in the sampled data and acquires the labeled data; the phase discrimination module determines a phase relation of a clock signal and a data signal and a theoretical moving direction of the clock signal in the data received by the high-speed serial interface receiving terminal according to the sampled data and the labeled data; and the delay chain adjusts the sampling position of the data acquisition module according to the theoretical moving direction of the clock signal so as to enable the sampling position to be located in a preset sampling area, thereby effectively reducing the bit error rate of the sampled data, only performing once sampling by using the data acquisition module, reducing the power consumption of the receiving terminal and improving the stability of the system.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and in particular, to a clock data recovery circuit and method. Background technique [0002] In high-speed serial data communication, in order to increase the rate of data transmission, the data signal and the clock signal synchronized with the data signal are respectively transmitted through different paths. Therefore, in the high-speed serial interface, the data signal and clock signal received by the receiving end need a clock and data recovery (Clock and Data Recovery, CDR) circuit to realign the positions of the two, that is, use the CDR circuit to judge and judge The phase relationship between the current clock signal and the data signal, adjust the clock signal to the most suitable position for sampling to reduce the sampling error rate and make the whole system work stably. [0003] At present, the edge detection method is a common data signal and clock signal alignm...

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a clock data recovery circuit and method to solve the problems of high power consumption, high bit error rate of sampled data, and low system stability of the existing CDR circuit at the receiving end of a high-speed serial interface and its corresponding edge detection method

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