Negative-voltage charge pump

Abstract

The invention discloses a negative-voltage charge pump. The negative-voltage charge pump comprises a voltage division circuit connected between the negative voltage output by the charge pump and a first reference voltage; the output partial voltage is used as a feedback voltage to be connected to the first input end of a first operational amplifier; the second input end of the first operational amplifier is grounded; the output end of the first operational amplifier is connected to the gate of a first NMOS transistor; the source of the first NMOS transistor is grounded; a drain outputs a clock control signal; the clock signal is input to the input end of the charge pump through a clock control circuit; the clock control signal is input to the clock control circuit to adjust the amplitude of the clock signal; a second comparator monitors the value of the clock control signal and enables a current path to be conducted to the first output end of the charge pump when the clock control signal is greater than the first bias voltage, thereby improving the total load current of the charge pump and lowering the clock control signal until the clock control circuit can correctly transmit the low-level value of the clock signal; and by virtue of the negative-voltage charge pump, the circuit stability can be improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a negative charge pump (Negative charge pump). Background technique [0002] like figure 1 As shown, it is a schematic diagram of an existing negative pressure charge pump. The negative pressure charge pump in the embodiment of the present invention includes: [0003] A voltage divider circuit 5, the voltage divider circuit 5 is connected between the negative voltage VNEG output by the charge pump 1 and the first reference voltage VREF0, the voltage divider circuit 5 outputs the negative voltage VNEG and the first reference voltage VREF0 The divided voltage is used as the feedback voltage VNEG_DIV. The voltage divider circuit 5 is composed of a first resistor string, figure 2 The first resistor string is formed by connecting multiple resistors R1 in series. [0004] The first reference voltage VREF0 is output by a reference voltage regulating circuit. figure 1 Among the...

AI Technical Summary

Problems solved by technology

[0014] Guarantee the capability of charge pump 1 at 100μA, but when the load current is only 1μA, the potential of VGNDA will be raised (about 0.6v), and the clock signal link, that is, the clock control circuit 2 cannot transmit CLK / CLKB correctly low level, resulting in abnormalities such as charge backflow on the capacitor of the Boost Stage, that is, the charge pump 1

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