Structure for improving stacking mounting of multiple chips and technological method of structure

Abstract

The invention discloses a structure for improving stacking mounting of multiple chips and a technological method of the structure. The structure comprises a frame base material (1); the front side ofthe frame base material (1) is provided with a lower layer chip (2) and an H-shaped support (6); an upper layer chip (3) is arranged on the front side of the H-shaped support (6); the frame base material (1), the lower layer chip (2) and the upper layer chip (3) are connected through welding lines (7); the lower layer chip (2), an upper layer chip (3), the H-shaped support (6) and the welding lines (7) are coated with a plastic packaging material (8). The invention provides the structure for improving stacking mounting of the chips and the technological method of the structure. The space utilization rate can be increased as much as possible in the same size of packaging, more convenient layout can be achieved, the problem that partial areas of the upper layer chip are arranged in a suspended mode is avoided, and the problem that part of a routing area of the lower layer chip is covered with the upper layer chip is avoided.

Description

technical field [0001] The invention relates to a structure for improving multi-chip stacking chip loading and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] At present, the development trend of semiconductor products is miniaturization and densification, installing as many chips as possible in the smallest possible area, reducing space occupation, and improving space utilization, and the packaging required by customers generally has size requirements, so the product's The package size is limited. For the same package size, multi-chip stacking can effectively reduce the package size and meet the current development trend. There are some problems with multi-chip packaging. At present, there are the following types: [0003] 1. When loading multiple chips, the loading area is not large enough to meet the conditions. At this time, the chip or frame needs to be redesigned, and the required requirements may not...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide an improved multi-chip stacking chip loading structure and its process method in view of the above-mentioned prior art. In a limited space, it can effectively enhance the ability of multi-chip chip loading, increase the space Utilization rate, avoiding the problem of chip breakage due to insufficient strength in the suspended wire bonding area, and also avoiding the problem that part of the wire bonding area of ​​the lower chip is easily covered by the upper chip due to insufficient space

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