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Template convolution implementation method and system based on FPGA (Field Programmable Gate Array)

An implementation method and system implementation technology, applied in the field of image processing, can solve the problems that traditional methods can no longer meet the requirements, and achieve the effect of improving convolution processing results and improving processing efficiency

Inactive Publication Date: 2018-02-02
SHENZHEN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitation of CPU or DSP speed, for high-speed real-time design, traditional methods can no longer meet the requirements

Method used

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  • Template convolution implementation method and system based on FPGA (Field Programmable Gate Array)
  • Template convolution implementation method and system based on FPGA (Field Programmable Gate Array)
  • Template convolution implementation method and system based on FPGA (Field Programmable Gate Array)

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Embodiment 1

[0020] Embodiment 1 based on the invention, a method for implementing template convolution based on FPGA, comprising the steps of: obtaining the data bit width of the image data, selecting a register set corresponding to the depth based on the data bit width; obtaining the image data and storing it in the The register group is used to obtain the convolution coefficient and store it in ROM; obtain the selection parameters used to associate the register group with the convolution coefficient; extract the data stored in the register group and the corresponding convolution coefficient and perform multiplication, based on the adder group The results of the multiplication operations are summed to implement a convolution operation.

[0021] The method based on the embodiment further includes: selecting a shift register group corresponding to the depth based on the data bit width, the shift register group is used to obtain image data, and the register group obtains image data from the ...

Embodiment 2

[0032] Embodiment 2 based on the invention, a template convolution implementation system based on FPGA, including: a parameter input module, used to obtain the data bit width of the image data, and select a corresponding depth register set based on the data bit width, also used for Obtain the shape and size of the convolution window, and automatically generate a corresponding convolution operation unit based on the parameters; the data input module is used to obtain image data and store it in the register set, obtain the convolution coefficient and import it into ROM; the calculation module uses To obtain selection parameters for associating the register set with the convolution coefficient; the calculation module is also used to extract the data stored in the register set and the corresponding convolution coefficient and perform multiplication, and perform the multiplication operation based on the adder set The results are added together to implement the convolution operation....

Embodiment 3

[0037] Based on the embodiment 3 of the invention, the process of realizing the convolution of FPGA is realized:

[0038] Such as figure 1 The basic structure of the FPGA shown includes a central control unit, an input unit (that is, a data interface), a line buffer unit (composed of shift registers), a convolution window unit (register bank), and a convolution operation unit (acquiring data from the register bank) and perform multiplication), addition tree unit (adder group), template parameter interface (ie data interface or data input terminal), convolution coefficient interface (ie ROM, used to store multiplication coefficients) and output unit; wherein, the input unit Connect the line cache unit, the line cache unit is connected to the convolution window unit, the convolution window unit is connected to the convolution operation unit, the convolution operation unit is connected to the addition tree unit, and the addition tree unit is connected to the output unit; the temp...

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Abstract

The invention discloses a template convolution implementation method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps that: obtaining the data bitwidth of image data, and selecting a register group of corresponding depth on the basis of the data bit width; obtaining the image data, storing the image data into the register group, obtaining a convolution coefficient, and storing the convolution coefficient into an ROM (Read Only Memory); obtaining a selection parameter used for associating the register group with the convolution coefficient;and extracting data stored in the register group and the corresponding convolution coefficient, and carrying out multiplication, and adding the results of the multiplication on the basis of a summatorto realize the convolution operation. The system is used for executing the corresponding method. the register group matched with the image data is selected to store the data, the ROM is selected to store the convolution coefficient, the multiplication is carried out through the corresponding relationship between the register and the convolution coefficient, an add operation of a product is carried out through the summator to realize the convolution operation, a convolution processing result can be improved, and processing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of image processing, in particular to an FPGA-based template convolution implementation method and system. Background technique [0002] In digital image processing, image processing in spatial domain is an important method. Some common spatial filtering operations, including linear and nonlinear, are often involved in important operations that are image convolution operations. Since the convolution operation requires a very large amount of multiply-add operations, it takes too long to process high-resolution images. The traditional implementation method is to use a general-purpose CPU or DSP as a processor, and perform template convolution operations through a pipeline. Due to the limitation of CPU or DSP speed, for high-speed real-time design, traditional methods can no longer meet the requirements. Contents of the invention [0003] In order to solve the above problems, the present invention provides...

Claims

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Application Information

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IPC IPC(8): G06F17/15G06T1/20
CPCG06F17/153G06T1/20
Inventor 李东敖晟田劲东田勇
Owner SHENZHEN UNIV
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