Top select gate cut etching process

Abstract

The invention provides a top select gate cut etching process, which preposes the top select gate cut etching process, set behind the forming of ON stacking structure and before the forming of a step structure. As the core storage area is quite flat when the ON stacking structure is just formed, and the thickness difference between the core storage area and the edge area, and between the wafer center and the edge is small, the precision of the following top select gate cut etching process is easier to control. The problem that the etching precision of the top select gat cut due to surface height difference generated by the formation of the step structure and the chemical mechanical planarization (CMP) is difficult to control, and the unexpected damage to the lower layer of silicon nitride can be resolved. Accordingly, the subsequent gate shaping precision can be higher, and the product can have better resistance performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a 3D NAND flash memory structure, in particular to an etching process method for avoiding damage to a silicon nitride layer during tangential etching of a top layer selection gate. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Among them, 3D NAND takes its small si...

AI Technical Summary

Problems solved by technology

However, the technical limitation of the chemical mechanical polishing process (CMP) in the S3 step will cause the surface after planarization to still exist between the highest point and the lowest point. The difference in height, especially between the center and edge of the wafer, and the center and edge of the core storage area is also very different. In fact, in the ON stack structure, the oxide interlayer dielectric layer 21 and silicon nitride The thickness of the sacrificial dielectric layer 31 is also The order of magnitude, which leads to the existence of height difference due to insufficient CMP process will affect the etching accuracy of the top select gate tangent (Top Select GateCut) channel, resulting in unavoidable silicon nitride sacrificial dielectric layer under the oxide 31, such as the etching condition of the channel 62, and there will also be insufficient etching, such as the etching condition of the channel 63

[0013] The etching precision of the top select gate cut (Top Select Gate Cut) channel will further affect the precision of the back-end process (Back End of Line, referred to as BEOL), resulting in some parts of the tungsten gate being too thin, and some places If it is too thick, part of the tungsten needs to be removed, and if the tungsten gate is too thin, it will directly lead to too high resistance and affect the performance of three-dimensional (3D) flash memory.

Images