A method for equivalence testing of combinational logic circuits

Abstract

The invention discloses an equivalence detection method of a combinational logic circuit. The method comprises the steps that a logic coverage equivalence detection problem is divided into circuit including detection sub-problems by expanding a complementary minor concept, complementary minors of all product terms of one circuit expression to the other circuit expression are computed one by one, then whether or not the complementary minors are tautologies is judged on the basis of construction of Shannon structure charts of the complementary minors of all the product terms, and finally whetheror not a coverage equivalent relationship exists between two circuits is determined according to the judgment result of the tautologies. The equivalence detection method has the advantages that a logic function is subjected to decomposition and order reducing treatment by computing the complementary minors of the product terms, accordingly the coverage equivalence verification speed is increased,the operability and the detection efficiency are high, and the memory explosion problem cannot happen. The experimental structure indicates that the equivalence detection method is stable and effective, and the testing result of the circuits which are obtained through three algorithms integrated by EXPRESSO software indicates that the equivalence detection method has the remarkable speed advantage compared with two detection algorithms based on a truth table and a BDD.

Description

technical field [0001] The invention relates to a detection method, in particular to a combinational logic circuit equivalence detection method. Background technique [0002] The logic equivalence test aims at the equivalence test of two combinational circuits with different logic layer expressions, and checks whether they realize the same logic function according to the given logical expressions of the two combinational circuits. At present, the equivalence detection methods of combinational logic circuits mainly include algebraic method, truth table judgment method and functional method. [0003] The algebraic method is an intuitive method to test the equivalence of combinational logic circuits. This method uses the basic formula of logic algebra to process the logical expressions of two combinational circuits. If the same result can be obtained, the logical expressions of the two combinational circuits are logically equivalent. However, due to the large number of basic ...

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Problems solved by technology

This method does not have the problem of operability. Although the detection efficiency has been improved compared with the truth table determination method, it still cannot meet the needs of current ultra-large-scale circuits, and this method will face memory explosion under certain input variable sequences. The problem

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