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improved power mos

A device and semiconductor technology, applied in the field of semiconductor devices, can solve problems such as reducing the width of the embedded gate

Active Publication Date: 2022-05-17
NEXPERIA BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, trench gate technology offers some disadvantages due to the need to reduce the width of the embedded gate when low voltage configurations are desired

Method used

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Embodiment Construction

[0014] Many well-known manufacturing steps, components, and connectors have been omitted or not described in detail in the specification so as not to obscure the present disclosure.

[0015] figure 1 A schematic diagram depicting a cross-sectional view of a device 100 fabricated using a process described later in this document. The device 100 includes a gate electrode 112 , a RESURF plate 114 , a source region 102 , a body region 104 , a gate dielectric 106 , and a trench 110 filled with a dielectric 108 .

[0016] One way to fabricate such a device is to fabricate the gate electrode in a shallow trench and then create a RESURF plate by implanting the p-type RESURF region with high energy to make the RESURF plate deeper (to achieve a high breakdown voltage (BV dss )). However, as the energy is increased, the implanted species will infiltrate the implant mask, which is placed in place to protect areas other than the area through which the RESURF plate is created. This penetr...

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PUM

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Abstract

An improved power MOS. A process for fabricating a device is disclosed. The process includes: forming an epitaxial layer of a first conductivity type on a substrate; forming a first vertical portion of a second conductivity type in the epitaxial layer; creating a first vertical trench by vertical etching close to the first vertical portion; A first type oxide fills the first vertical trench; a second vertical trench is formed in the first vertical trench. The second vertical trench is defined by the first type oxide in the first vertical trench. The process further includes: forming a second type oxide on the inner wall of the second vertical trench; and filling the second vertical trench with polysilicon. In a second vertical portion of the epitaxial layer vertically adjacent to the first vertical trench, a body region is created by implanting ions of the first conductivity type, and a source region is created by implanting ions in a top layer of the body region.

Description

technical field [0001] The present disclosure relates to the field of semiconductor devices, and more particularly, to improved power MOSs. Background technique [0002] Trench gate technology is commonly used to improve breakdown voltage characteristics in semiconductor devices, especially high voltage devices. In trench gate technology, the gate is vertically buried in the source, usually separated by an isolation cap. Other advantages of trench gate technology include reducing Junction-Gate Field Effect Transistor (JFET) effects, which may be undesirable in at least some applications. However, trench gate technology offers some disadvantages due to the need to reduce the width of the embedded gate when low voltage configurations are desired. The reduced surface field (RESURF) technique is one of the most widely used methods for designing lateral high voltage, low on-resistance devices. This technology allows the integration of bipolar and MOS transistors with high volt...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/063H01L29/66734H01L29/7813H01L29/401H01L29/42368H01L29/0634H01L29/0696H01L29/1095H01L29/407H01L29/408
Inventor 史蒂文·托马斯·皮克
Owner NEXPERIA BV
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