Approximate circuit logic comprehensive optimization method based on evolution strategy

Abstract

The invention discloses an approximate circuit logic comprehensive optimization method based on an evolution strategy. Three parameters which are circuit area, power consumption and logic function ratio can be simultaneously optimized, to find out maximum alternating gains and losses between a circuit logic function and the area / power consumption. The optimization method based on evolution has thecapability of solving nonlinear problems, and an approximately optimal solution is found within a large search space.

Description

technical field [0001] The invention relates to an approximate circuit logic synthesis optimization method based on an evolution strategy. Background technique [0002] As VLSI fabrication technology has approached the nanometer scale, the dramatic advances in most circuit properties, especially latency and yield, have begun to taper off. One of the main reasons for this trend is the increase of non-ideal factors in the circuit, such as the probability of circuit defects and the generation of circuit variation in the industrial production process. In order to alleviate the influence of this non-ideal factor, researchers have proposed the concept of error tolerance and defect tolerance, but this technology has a great disadvantage-they require additional hardware, so compared with other circuits in the past , which is more complex. Therefore, the concept of fault tolerance is born: that is, while simplifying the circuit, it does not affect the operation of the circuit itsel...

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Problems solved by technology

The double-covered approximate circuit proposed by Sierawski et al. to reduce the soft error rate, after selecting the error-shielding space, synthesizes and optimizes the approximate circuit by means of minimum item sharing and adding irrelevant items; Shin et al. proposed a minimum item compensation method Realize the logic simplification of the circuit, but this method makes the logic of the approximate circuit more complicated in some cases. When changing from 0 to 1, a redundant minimum item is added, and when changing from 1 to 0, the original circuit reaches Increased Cube Complexity for Minimum Coverage

These methods are still based on the two-level logic expression of the circuit, and the scalability is poor

For the logic masking model based on one-way approximation circuit and the timing masking model based on two-way approximation circuit, Choudhury et al. proposed a technology-independent Boolean network and cube selection method for the synthesis of approximate circuits. In logic error masking, their method It is necessary to ensure the correctness of the approximation through iteration; Sánchez-Clemente et al. used an approximate circuit synthesis method based on testability analysis. Through the analysis of nodes, the logic value of the node is fixed to realize the approximate circuit. The fine-grained logic synthesis of this method makes the calculation The complexity increases, and at the same time, there is a lack of optimization of the approximate circuit logic; Yuan et al. proposed an approximate circuit shielding method for timing errors, and determined the logic with primary inputs (uncontrollable inputs) in the path through the analysis of key triggers and paths Gates, an approximate circuit is generated by removing gates that do not have primary inputs. For large-scale circuits, determining unnecessary inputs to logic gates is computationally expensive, and no solution is mentioned in the study; Shin et al. In order to insert fixed faults into the original circuit nodes to achieve two-way simplification to obtain approximate circuits, under the constraints of the fault tolerance threshold of the application layer, circuit logic optimization is realized through greedy heuristic iterations. This method is suitable for applications that have flexible requirements for system output accuracy; The evolutionary hardware method of Sekanina et al. obtains an approximate circuit by removing the logic gates on the basis of the evolutionary original circuit, and selects the circuit with the opposite optimal benefit as the result. Manual intervention is required in the process of large-scale circuit design, and scalability problems are still faced. The limited scalability has always been the biggest obstacle hindering the practical application of evolutionary hardware technology; the method of Venkataramani et al. can be combined with the existing traditional logic method , but its scalability has not been verified

In the above-mentioned multi-level logic synthesis methods, some algorithms solve the timing error problem, such as the algorithm proposed by Yuan, which cannot be directly shielded from logic errors; some algorithms have high computational complexity

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