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A Method for Reducing Computational Complexity of Equations in Integrated Circuit Design

A computing complexity, integrated circuit technology, applied in CAD circuit design, complex mathematical operations, special data processing applications, etc., can solve the problems of low optimization efficiency of capacitor devices and insufficient optimization of equations, shortening simulation time, The effect of reducing coupling and reducing complexity

Active Publication Date: 2020-06-16
SHENZHEN HUADA EMPYREAN TECH CO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

In particular, the present invention provides a special optimization method for capacitor devices in order to solve the problem that the optimization efficiency of capacitor devices in current integrated circuit automation products is not high, which leads to insufficient optimization of equations.

Method used

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  • A Method for Reducing Computational Complexity of Equations in Integrated Circuit Design
  • A Method for Reducing Computational Complexity of Equations in Integrated Circuit Design
  • A Method for Reducing Computational Complexity of Equations in Integrated Circuit Design

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Embodiment Construction

[0019] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0020] figure 1 It is a working flowchart of the method for reducing the computational complexity of equations in integrated circuit design according to the present invention. The following will refer to figure 1 , to describe the method for reducing the computational complexity of the equation system in the integrated circuit design of the present invention.

[0021] First, in step 101, start to optimize and enter into an optimization program.

[0022] At step 102, a tolerance for capacitance optimization is determined.

[0023] In this step, all capacitive devices to be optimized are traversed first, the properties of the modules where they are located are judg...

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Abstract

The invention discloses a method of reducing calculation complexity of equations in integrated-circuit design. The method is characterized by including the following steps: 1) determining tolerance ofcapacitance optimization; 2) traversing all capacitance devices; and 3) carrying our disconnection or a split on each traversed capacitance device according to the tolerance of capacitance optimization. According to the method of reducing the calculation complexity of the equations in integrated-circuit design of the invention, dimensionality of the equations can be reduced, the number of non-zero elements in a sparse matrix can also be decreased, coupling among rows in the equations can be reduced at the same time, thus the calculation complexity of the equations is reduced, and an overall design cycle of an electronic circuit is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit automation product design, in particular to a method for reducing the computational complexity of equations in integrated circuit design. The invention is a method for optimizing the equation group in integrated circuit automation products, especially for the optimization of post-simulation circuits. Background technique [0002] The scale of equations in electronic circuits is an important factor restricting the performance of integrated circuit automation products. How to optimize the equations and how to reduce the computational complexity of the equations is a hot topic in current electronic circuit design. As the process continues to progress toward the nanoscale, the scale of the circuit is also expanding rapidly, and the scale of the corresponding equations is also increasing rapidly. If no optimization is carried out, the time and space consumption of the entire simulation will be great...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/39G06F17/15
CPCG06F17/15G06F30/39
Inventor 刘琳邵雪程明厚周振亚吴大可
Owner SHENZHEN HUADA EMPYREAN TECH CO LTD
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