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Non-volatile memory

A non-volatile, memory technology, applied in the field of memory, can solve the problems of oxide layer breakdown, inability to operate non-volatile memory, etc., and achieve the effect of preventing oxide layer breakdown and preventing read current from being too low

Active Publication Date: 2018-05-01
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, in the existing non-volatile memory, the input and output elements are generally used as selection transistors, so it is impossible to operate the non-volatile memory in a low power and high speed manner.
[0006] In addition, if a logic element (core device) is used as the selection transistor in order to achieve low-power and high-speed operation, the selection transistor will be subjected to excessive stress when the non-volatile memory is programmed. The situation that causes oxide breakdown (oxide breakdown)

Method used

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Embodiment Construction

[0055] figure 1 It is a top view of a non-volatile memory according to an embodiment of the present invention. exist figure 1 In order to clearly describe the structure of the non-volatile memory, the illustration of the isolation structure and the dielectric layer is omitted. Figure 2A for along figure 1 The cross-sectional view of the I-I' section line. Figure 2B for along figure 1 Sectional view of section line II-II'. Figure 2C for along figure 1 Sectional view of section line III-III'.

[0056] Please also refer to figure 1 and Figure 2B , the non-volatile memory 10 includes a substrate 100 , a floating gate transistor 102 , a selection transistor 104 and a stress relief transistor 106 . The floating gate transistor 102 , the select transistor 104 and the stress relief transistor 106 are disposed on the substrate 100 and connected in series. The stress release transistor 106 is located between the floating gate transistor 102 and the select transistor 104 , ...

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Abstract

The invention discloses a non-volatile memory comprising following components. A floating gate transistor, a select transistor and a stress relief transistor are disposed on the substrate and are connected in series with one another. The stress relief transistor is located between the floating gate transistor and the select transistor. The stress relief transistor has a stress release ratio represented by Equation (1). The lower limit of the stress relief ratio is determined by the withstand drain voltage of the stress relief transistor of the non-selective non-volatile memory during the programming operation. The upper limit of the stress relief ratio is determined by the readable drain current of the selected non-volatile memory during the read operation. The non-volatile memory can effectively reduce the stress experienced by the select transistor. Stress Releasing Ratio = Channel Length of Stress Relief Transistor / Gate Dielectric Thickness of Stress Relief Transistor (1).

Description

technical field [0001] The present invention relates to a memory, and in particular to a non-volatile memory. Background technique [0002] When the semiconductor enters the deep sub-micron (Deep Sub-Micron) manufacturing process, the size of the element is gradually reduced. For the memory element, it means that the size of the memory cell is getting smaller and smaller. On the other hand, as the data that information electronic products need to process and store increases day by day, the storage capacity required in these information electronic products will also become larger and larger. For such a situation where the size is reduced but the memory capacity needs to be increased, how to manufacture memory elements with reduced size, high integration, and quality is a common goal of the industry. [0003] The non-volatile memory element has become a memory element widely used in personal computers and electronic devices because of its advantage that the stored data will n...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11521H10B41/30
CPCH10B69/00
Inventor 徐德训
Owner EMEMORY TECH INC