Fabrication process of ultra-fine porous structure
A pore and process technology, applied in the field of ultra-fine pore structure fabrication process, can solve the problems of affecting pore size, easy shrinkage, and loss of thickness of silicon dioxide sidewall layer.
Active Publication Date: 2021-01-26
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
The silicon dioxide layer produced by low-temperature atomic layer deposition has two unfavorable factors, that is, the wet etching rate is fast and it is easy to shrink at high temperature. Due to the above two unfavorable factors, the wet cleaning step and the sticky In the deposition step of the combined layer, the thickness of the silicon dioxide sidewall layer will be more lost, which will eventually affect the size of the hole
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[0025] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0026] The basic idea of the present invention is to increase the step of rapid high-temperature annealing after depositing and forming the silicon dioxide layer in the process of forming the ultra-fine pore structure size through the silicon dioxide sidewall technology to improve the thickness of the silicon dioxide layer sidewall. Quality, reducing the impact of the subsequent forming process on it.
[0027] Such as figure 1 S...
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The invention relates to a manufacturing process of an ultra-fine pore structure, comprising the following steps: providing a chip structure; performing etching, forming a contact hole in the top layer deposition film of the chip structure, exposing the upper surface of the tungsten plug in the second top layer deposition film In the contact hole; depositing silicon dioxide into the contact hole, forming a silicon dioxide deposition layer on the side wall of the contact hole and the upper surface of the tungsten plug, thereby forming an ultrafine hole; performing high-temperature annealing on the silicon dioxide deposition layer; Perform wet cleaning to remove part of the silicon dioxide deposition layer on the upper surface of the tungsten plug in the ultra-fine hole; deposit an adhesive material into the ultra-fine hole to form an adhesive layer; deposit tungsten into the ultra-fine hole to make the tungsten The remaining pores filled with ultrafine pores form an ultrafine pore structure. In the present invention, by adding the high-temperature annealing step of the silicon dioxide side wall in the formation process of the ultra-fine pore structure, the influence of the subsequent wet cleaning and adhesive material deposition steps on the thickness of the side wall is reduced, and the size of the ultra-fine pore structure is ensured .
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing technology, in particular to the manufacturing technology of ultrafine hole structure. Background technique [0002] With the continuous development of semiconductor technology, the current memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure. The technology research and development of 3D NAND is one of the mainstreams of international research and development. [0003] The structure of 3D NAND is usually realized by depositing multi-layer films and then etching to form contact holes. The contact holes are used to connect the wiring layer in the lower layer and the wiring layer in the upper layer in 3D NAND. In recent processes, and in order to improve memory performance, the diameter of contact holes has become ultra-fine. [0004] In the process of ultra-fine holes, silicon dioxide sidewall technology i...
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IPC IPC(8): H01L27/11524H01L27/11526H01L21/768H10B41/35H10B41/40
CPCH01L21/768H01L21/76853H01L21/76864H10B41/35H10B41/40
Inventor 王喆王鹏程高晶
Owner YANGTZE MEMORY TECH CO LTD