prefetch block

Abstract

Techniques related to prefetching instruction blocks are disclosed. In one example of the disclosed technology, a processor includes a block-based processor core for executing a program including a plurality of instruction blocks. Block-based processor cores may include prefetch logic and local buffers. The prefetch logic may be configured to receive a reference to a predicted instruction block and determine a mapping of the predicted instruction block to one or more lines. The local buffer may be configured to selectively store portions of the predicted instruction block and provide the stored portion of the predicted instruction block as control of the program passes to the predicted instruction block along the predicted execution path.

Description

Background technique [0001] Due to the continued transistor scaling predicted by Moore's Law, microprocessors have benefited from continued increases in transistor count, integrated circuit cost, manufacturing capital, clock frequency, and energy efficiency, while the associated processor instruction set architecture (ISA) has Little changes. However, the benefits realized from the lithographic expansion that has driven the semiconductor industry for the past 40 years are slowing or even reversing. The Reduced Instruction Set Computing (RISC) architecture has been the dominant paradigm in processor design for many years. Out-of-order superscalar implementations have not shown consistent improvements in area or performance. Thus, there is ample opportunity for processor ISA improvements to scale performance improvements. Contents of the invention [0002] A method, apparatus, and computer-readable storage device for prefetching instruction blocks for a block-based processo...

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Problems solved by technology

Therefore, there is ample opportunity for processor ISA improvements to scale performance improvements

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