An online upgrade method of FPGA based on nios II

Abstract

The invention relates to the field of FPGA chips, and discloses a NIOS II-based FPGA online upgrade method, so that the FPGA can be reconfigured online in an AS configuration mode without resorting to an external controller chip. The IP core embedded in the NIOS II processor of the present invention is used as a controller, and integrates external serial ports and network ports; when the system is powered on or reset, the NIOS II processor starts the timer and closes the watchdog program. If the internal NIOS II processor does not receive data from the serial port or network port, it reads the FPGA configuration file data from the configuration FLASH chip and enters the user mode; if it receives data and the received data is upgrade data, write the upgrade data to Enter and configure the FLASH chip, start the watchdog program after receiving and writing the upgrade data, trigger the system reset, and complete the online upgrade of the FPGA. The present invention is applicable to FPGA configuration.

Description

technical field [0001] The invention relates to the field of FPGA chips, in particular to an FPGA online upgrade method based on NIOS II. Background technique [0002] FPGA has the characteristics of flexible programming and can be used as a development platform for the prototype design of special satellite navigation chips. The configuration data of the FPGA based on the SRAM process will be lost after power-off, and it is necessary to add an external configuration FLASH chip to save the FPGA configuration data, such as EPCS64, EPCQ256, etc. After power-on, the configuration data stream needs to be read from the configuration FLASH chip and loaded into the FPGA, so that the FPGA can run normally. [0003] Commonly used FPGA configuration methods include active serial mode (AS) and passive serial mode (PS). In AS mode, FPGA provides configuration clock signal DCLK, and in PS mode, other devices provide configuration clock signal DCLK to FPGA. AS configuration mode box fig...

AI Technical Summary

Problems solved by technology

[0006] In the existing AS configuration mode, the JTAG port of the FPGA needs to be connected every time the FPGA is upgraded. After the FPGA is integrated into the entire system, the JTAG port is usually not reserved for the external interface of the system, and it needs to be disassembled when upgrading, which is time-consuming and laborious.

The existing PS configuration mode can reconfigure FPGA through the external interface of the system such as serial port and network port, which solves the problem of inconvenient upgrade in AS mode

However, at present, the density of FPGA is increasing, and the configuration data is also increasing, reaching tens of megabits or even hundreds of megabits. Multiple flash chips are required to store these configuration data, resulting in increased complexity and additional hardware costs, such as FLASH chip and controller chip cost

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