Writing method for resistive random access memory based on crosspoint array

A resistive memory and cross-point technology, applied in the field of information storage, can solve the problem of not fully considering the write delay distribution of the cross-point array, and achieve the effect of being beneficial to address mapping, reducing write delay differences, and improving throughput.

Active Publication Date: 2018-05-18
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

Therefore, the row-by-row region partitioning, addressing, and addressing schemes of traditional compatible DRAMs do not fully account for the uneven write latency distribution in cross-point arrays

Method used

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  • Writing method for resistive random access memory based on crosspoint array
  • Writing method for resistive random access memory based on crosspoint array
  • Writing method for resistive random access memory based on crosspoint array

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Embodiment Construction

[0059] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0060] Such as figure 2 Shown, the inventive method comprises:

[0061] (1) Voltage bias based on effective current path: Divide one cross-point array into four logical units (sub-arrays). According to the physical address of the accessed unit, the peripheral circuit is dynamically configured so that the memory units at different positions in the cross-point array (that is, in different sub-a...

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Abstract

The invention discloses a writing method for a resistive random access memory based on a crosspoint array, belonging to the field of information storage. The method of the invention increases effective voltage and reduces write delays by dynamically selecting the shortest voltage drop path; one regional division manner is employed to reduce differences among write delays in each area, so write delays in each area are reduced, and unit-level parallelism is guaranteed at the same time; the mapping between physical addresses and unit locations is established by employing an addressing mode, so write delays increase with the physical addresses, which facilitates optimization of address mapping, memory allocation and compilation; a parallel addressing circuit system is provided to speed up theaddressing process; and SET and RESET processes are overlapped for units in different rows and columns in virtue of a specific voltage bias mode, and row-level parallelism in the crosspoint array is developed. The method of the invention can reduce the write delays of the resistive random access memory, increase write bandwidth, and decrease the power consumption of writing.

Description

technical field [0001] The invention belongs to the field of information storage, and more particularly relates to a writing method of a resistive variable memory based on a cross-point array. Background technique [0002] DRAM has been used as memory for decades. However, it is difficult to further reduce the process of DRAM after it is reduced to tens of nanometers, and its cell access delay has been maintained at tens of nanoseconds and it is difficult to further reduce it. In addition, DRAM is a kind of volatile memory, and the energy consumption cost caused by its refresh operation cannot be ignored. These problems make it increasingly difficult to build large-capacity, low-latency, and low-power memory with DRAM. The emergence of emerging non-volatile memory has brought hope to the development of memory. Among them, resistive random-access memory (RRAM) is due to its smaller cell size (<10nm), longer write endurance (>10 10 cycles), higher on / off resistance r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10G11C16/10
CPCG11C7/1078G11C16/10
Inventor 冯丹童薇刘景宁汪承宁张扬李艺林
Owner HUAZHONG UNIV OF SCI & TECH
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