Hash hybrid acceleration system and method for applying same for hash joins

Abstract

The invention discloses a hash hybrid acceleration system and a method for applying the same for hash joins. The system comprises a hash partition accelerator and a host processor, wherein the hash partition accelerator is integrated on a memory, is used for accelerated processing of a hash join partition period, and comprises a hash unit, a histogram unit and a shuffle unit, the hash unit is usedfor reading multiple tuples from a relation table of a partition block in the memory, and parallelly processing keys of the tuples to generate multiple hash indexes, the histogram unit is used for parallelly updating multiple copies which are stored in histogram data in the histogram unit according to the hash indexes, and integrating all the updated copies into a form with data consistency; theshuffle unit is used for determining the positions of all the tuples stored in a target address array according to the hash indexes, and copying the tuples in the relation table to a target array; thehost processor is used for processing a build period and a probe period of hash joins. Compared with an existing processor, the hash hybrid acceleration system can greatly improve the energy efficiency of hash joins.

Description

technical field [0001] The disclosure relates to the field of computer systems, and further relates to a hash mixing acceleration system and a hash connection method using the hash mixing acceleration system. Background technique [0002] The first factor to consider when designing a modern computer system is power consumption. To improve energy efficiency, hardware accelerators such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and custom accelerators have been widely used in industry. With the advent of processing technology close to the data, integrating hardware accelerators into the dynamic random access memory (DRAM) stack to reduce the cost of data movement has become a new system design idea. The basic idea is to use 3D stacking technology to vertically integrate some logic dies including accelerators and multiple DRAM dies into one chip. However, the number and types of accelerators that can be integrated into DRAM are limited due to ...

AI Technical Summary

Problems solved by technology

However, the number and types of accelerators that can be integrated into DRAM are limited due to the limitations of 3D stacked DRAM in terms of area, power consumption, heat dissipation, and manufacturing.

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