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Method of determining arrangement of at least one circuit for a reconfigurable logic device

A logic device and reconfiguration technology, applied in configuration CAD, CAD circuit design, constraint-based CAD, etc.

Active Publication Date: 2021-06-11
FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG EV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, programmers frequently use this procedure for all different kinds of compiled languages, and the effect on the result is often limited to common compiler options, such as the specification of optimization levels

Method used

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  • Method of determining arrangement of at least one circuit for a reconfigurable logic device
  • Method of determining arrangement of at least one circuit for a reconfigurable logic device
  • Method of determining arrangement of at least one circuit for a reconfigurable logic device

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Embodiment Construction

[0037] Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0038] Therefore, while further examples are capable of various modifications and alternative forms, some specific examples thereof are shown in the drawings and will be described in detail later. However, this detailed description does not limit the additional examples to the specific forms described. Additional examples may cover all modifications, equivalents, and substitutions falling within the scope of the disclosure. Like reference numerals refer to like or similar elements throughout the description of the drawings, which elements may be implemented the same or in modified form when compared with each other while providing the same or similar functions.

[0039] It will be understood that when an element is referred to as being "conn...

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PUM

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Abstract

A method of determining an arrangement for at least one circuit of a reconfigurable logic device. The method includes the step of obtaining (110) information related to at least one circuit comprising a plurality of blocks and a plurality of connections between the plurality of blocks. A plurality of blocks includes a plurality of logical blocks. The method also includes computing (120) a circuit diagram based on information related to at least one circuit. A circuit graph includes multiple nodes and multiple edges. The plurality of nodes represents at least a subset of the plurality of blocks of the at least one circuit, and wherein the plurality of edges represents at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit. The method also includes determining (130) a force-directed layout of the circuit diagram. Force-directed layout is based on attraction and is based on repulsion between blocks, which is based on connections between blocks. The method also includes determining (140) placement of the plurality of logic blocks onto the plurality of available logic cells of the reconfigurable logic device based on the force-directed layout of the circuit diagram.

Description

technical field [0001] Examples relate to methods and computer programs for determining an arrangement of at least one circuit for a reconfigurable logic device, more particularly but not exclusively, based on force-directed layout. Background technique [0002] The compilation process is often considered a black box. Based on the input code, their task is to produce an executable version of the processing description. This transformation is necessary for any compiled programming language and execution environment. Thus, a compiler typically performs the task of converting an abstract description into concrete machine instructions. [0003] However, programmers frequently use this procedure for all different kinds of compiled languages, and the influence on the result is often limited to common compiler options, such as the specification of optimization levels. However, compiler development itself is a very interesting computer science discipline. The availability of dif...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392
CPCG06F30/392G06F30/18G06F30/34G06F2111/04G06F2111/20G06F30/347
Inventor D·菲尔德T·佐德曼
Owner FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG EV