A method for testing the interface state of a three-port silicon carbide-based power device

Abstract

A method for testing the interface state of a three-port silicon carbide-based power device. This method can simply and quickly extract the average interface state density at the interface between the junction field effect region and the gate oxide layer of the three-port silicon carbide-based power device. The frequency and amplitude of the external gate of silicon carbide-based power devices are fixed and the base voltage V 0 Varying pulse voltage or frequency and base voltage V 0 fixed while the amplitude V p The changing pulse voltage, the source is connected to the negative pole of the reverse bias voltage, the drain is connected to the positive pole of the reverse bias voltage, the drain is connected to the ammeter to detect the current, and the ammeter is connected in series in the loop composed of the drain, voltage source, and source, and a The current-voltage curve, the average distribution of the interface state along the junction field effect region can be obtained by calculating the peak current of the current-voltage curve through the formula. At the same time, the junction field effect region and the channel of the device can be judged by comparing the test curves before and after stress. The degradation of the interface of the gate oxide layer under stress.

Description

technical field [0001] The invention belongs to the field of reliability of power semiconductor devices, and in particular relates to an interface state testing method of a three-port silicon carbide-based power device. Background technique [0002] With the improvement of the performance and reliability requirements of power devices in the automotive industry and portable electronic systems, three-port SiC-based power devices stand out because of their high input impedance, low drive power, high switching speed, and good thermal stability. As a switching device, SiC-based power devices need to be turned on and off frequently. During the switching process, the current and voltage vary greatly. Under the influence of circuit parasitic parameters, current and voltage overshoots will occur, resulting in device breakdown and The interface characteristics of the device become worse, and the interface characteristics of the device seriously affect the performance of the device, su...

AI Technical Summary

Problems solved by technology

Because the interface state generated under external stress has the characteristics of non-uniform distribution, it is difficult to reliably and accurately measure the interface state generated by the device under external stress by the traditional capacitance (C-V) method. The invention provides a three Test method for interface state of SiC-based power devices with ports

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