System and method of improving performance of general GPU (Graphics Processing Unit)

Abstract

The invention discloses a system and a method of improving performance of a general GPU (Graphics Processing Unit). The system comprises a cache group pressure monitoring table, an access target blockarbitration unit and a remapping table, wherein the cache group pressure monitoring table is arranged in an on-chip memory of a mainstream multiprocessor for recording the reading and writing times of each cache group, and according to the recorded reading and writing times, the pressure state of each cache group is periodically updated; the access target block arbitration unit is used for arbitrating an access request according to the pressure state of the cache group and the remapping table, when a support group is searched for the request of a cache group with large pressure, the support group is searched, a searching result is obtained according to the cache group pressure monitoring table, and further, in the remapping table, the mapping relationship between the cache group with large pressure and the support group is built; and the remapping table is arranged in the on-chip memory of the mainstream multiprocessor for recording the mapping relationship between each high-frequencyvisited cache group and the support group, and the mapping is released through changing an effective status bit. Thus, the on-chip resource efficiency of the GPU can be improved.

Description

technical field [0001] The invention relates to the field of general graphics processor chip design, in particular to a system and method for improving the performance of a general graphics processor. Background technique [0002] Graphics processors have experienced tremendous growth in recent years as general-purpose and high-throughput devices. Relying on a large number of parallel threads and huge memory bandwidth, general-purpose graphics processors achieve superior performance. On-chip storage as a parallel thread and memory bridge is implemented using a very complex multi-level structure, including registers, shared memory, and data caches. Jing et al. According to the phenomenon of low utilization of internal registers and insufficient data caches in each stream multiprocessor in graphics processors, they proposed to fuse on-chip registers and caches, and integrate the two into one, so as to improve resource utilization. and to improve performance. [0003] Howeve...

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Problems solved by technology

[0003] However, the on-chip storage based on the fusion register file and data cache has its own unique characteristics: the on-chip fusion storage capacity of the set associative structure is large enough, and it is managed according to the cache method, and the register data needs to be protected first, which increases the burden on the cache between groups. access imbalance

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