Processor and instruction scheduling method

Abstract

The invention provides a processor and an instruction scheduling method, and belongs to the technical field of computers. The processor supports X interlaced threads, wherein X is an integer greater than 1. The processor comprises a decoding unit and a processing unit. The decoding unit is used for obtaining an instruction from each of Z predefined threads in each cycle period, decoding the Z obtained instructions to obtain Z decoding results and sending the Z decoding results to the processing unit, wherein each cycle period comprises X sending cycles, a decoding result is sent to the processing unit in each sending cycle, the decoding results repeatedly sent in multiple sending cycles by the decoding unit can exist in the Z decoding results, Z is greater than or equal to 1 and less thanX or Z is equal to X, and Z is an integer. The processing unit is used for executing the instructions according to the decoding results. According to the technical scheme provided by the method, the processing unit is fully utilized, so that high usage efficiency of the processing unit is ensured and the performance of the processing unit can be fully utilized.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a processor and an instruction scheduling method. Background technique [0002] Processors often use pipelining to speed up processing. If the instruction to be executed in the pipeline needs to rely on the execution result of the previous instruction, but the previous instruction has not been completed, the instruction cannot be executed immediately. At this time, the conflict caused can be called data hazard (data hazard) ), which in turn leads to delays in processing instructions. In the prior art, an interleaved multi-thread (Interleaved Multi-Threading, IMT) technology is used to solve the instruction processing delay caused by data hazard on the pipeline. [0003] The IMT technology is an instruction scheduling mechanism utilizing Thread Level Parallelism (TLP). Please refer to figure 1 , which shows a schematic diagram of an instruction scheduling process o...

AI Technical Summary

Problems solved by technology

[0008] The embodiment of the present application provides a processor and an instruction scheduling method to solve the problem that the existing processor using S-IMT technology cannot make full use of the data when the number of threads actually executed is less than the maximum number of threads it supports. path, resulting in a reduction in the use efficiency of the data path, and the problem that the performance is not fully utilized

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