Method for reducing power jitter of power supply in cold backup mode
A cold backup and mode technology, applied in data processing power supply, electrical digital data processing, instruments, etc., can solve problems such as power fluctuations, achieve the effect of simple structure, reliable design principle, and outstanding substantive features
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Embodiment 1
[0026] A method for reducing power jitter of a power supply in cold backup mode provided by the present invention is characterized in that it comprises the following steps:
[0027] S1: The PFC current loop adopts PI control, and the loop output is limited up and down to give the PFC duty cycle;
[0028] S2: The lower limit of the PFC loop output is set to a negative value less than 0; this negative value will participate in the next PI calculation;
[0029] S3: The negative value is sent to the PFC wave through a lower limit of 0, so that the minimum duty cycle of the PFC wave is 0.
Embodiment 2
[0031] In the step S2, PI output=KI*last PI output result+KP*this input amount.
Embodiment 3
[0033] The PFC current loop in the step S1 is a charge pump phase-locked loop, and the charge pump phase-locked loop includes a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) feedback divider (1 / N); constant between input phase and output phase.
[0034] When the frequency division factor of the feedback divider is set to N, the PLL can control the reference clock ω ref Do N multiplication.
[0035] When the input phase changes suddenly, the output of the closed-loop system follows the change of the input phase within the loop bandwidth.
[0036] The frequency and phase detector compares the input reference clock ω ref and feedback divider clock ω fb Between the phases, the UP and DN signals are obtained, and the UP and DN signals control the charging and discharging of the charge pump.
[0037] when ω ref Advance ω fb When , the UP signal opens the pull-up path to charge the low-pass filter LPF, so that...
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