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Wafer surface planarization method

A surface flattening and wafer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as poor results and inability to completely eliminate wafer surface nanotopography, and achieve easy operation and high efficiency. , the effect of simple process steps

Inactive Publication Date: 2018-11-02
ZING SEMICON CORP
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  • Claims
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Problems solved by technology

[0010] In view of the prior art described above, the purpose of the present invention is to provide a wafer surface planarization method, which is used to solve the poor effect of the wafer flattening method in the prior art and the inability to completely eliminate the surface nanometer surface of the wafer. shape problem

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Embodiment Construction

[0046] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] see Figure 1 to Figure 11 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the shape, quantity and proportion of each component can be changed arbitrarily during actual implementation, and...

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Abstract

The invention provides a wafer surface planarization method. The wafer surface planarization method comprises the following steps of 1) providing a wafer, wherein the wafer comprises a first surface and a second surface which are opposite to each other; 2) forming a curing planarization layer on the first surface of the wafer; 3) grinding the second surface of the wafer; 4) grinding the curing planarization layer and the first surface of the wafer to remove the curing planarization layer, and flattening the first surface of the wafer. By the wafer planarization method, surface nanometer morphology of a wafer surface can be thoroughly eliminated, and the wafer planarization method has the advantages of simple process step, relatively high efficiency and the like and is easy to operate.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a wafer surface planarization method. Background technique [0002] With the development of semiconductor process technology, surface nanotopography (nanotopography) has become an important focus after reaching the 0.25μm technology node; surface nanotopography refers to the deviation of 0.2mm to 20mm formed on the surface of the wafer. Specifically, it is the corrugated structure formed on the surface of the formed wafer during the wire cutting process. Surface nano-topography has a significant impact on the CMP process of shallow trench isolation structures. [0003] In recent years, several methods have been proposed to treat the wafers formed by slicing to remove surface nanotopography before wafer polishing, as follows: [0004] 1. Double Side Lapping [0005] The specific method of double-sided grinding is: place the wafer horizontally and use Al 2 o 3...

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Application Information

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IPC IPC(8): H01L21/304
CPCH01L21/304
Inventor 赵厚莹
Owner ZING SEMICON CORP
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