A Fast Locking Delay Locking Ring

Abstract

The invention discloses a fast locking delay locked loop, which comprises a phase detection module, a counting module, a delay module, a control module and a selection module. The phase detection module has two input ports, a phase state output port and a phase mark output port. Wherein, the two input ports of the phase detection module are respectively connected to the reference clock and the feedback clock, the phase state output port is connected to the input port of the control module, and the phase mark output port is connected to the input port of the counting module; the input port of the counting module is connected to the counting clock, counting The output port of the module is connected to the input port of the control module; the output port of the control module is connected to the input port of the selection module; the input port of the delay module is connected to the reference clock, the output port of the delay module is connected to the input port II of the selection module, and the output port of the selection module Output feedback clock signal. The invention has a simple structure and greatly improves the working efficiency of the delay locking ring.

Description

technical field [0001] The invention relates to the field of CMOS integrated circuit design, in particular to a fast-locked delay locked loop. Background technique [0002] With the development of CMOS integrated circuit technology, clock circuits play a very important role in both digital and analog integrated circuit design. However, PLL (Phasel Locked Loop) phase-locked loops are basically designed using analog circuits, and the circuit noise problem is relatively large, and the circuit design is difficult and the reusability is poor. The DLL (Delay Locked Loop) delay-locked loop, especially the all-digital DLL circuit, is more and more widely used because it is completed based on digital logic, the circuit noise performance is good, and the circuit has strong reusability. [0003] Moreover, in some circuit designs, not only strict requirements are placed on the clock frequency, but also the phase of the clock is also very concerned. For example, in TDC, the phase diffe...

AI Technical Summary

Problems solved by technology

The current DLL circuit generally adopts the one-by-one adjustment method and the successive approximation control method; if the one-by-one adjustment method is adopted, the circuit lock time will be longer, and the design of the successive approximation control method is relatively difficult.

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