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Data processing method for hardware acceleration of convolutional neural network

A convolutional neural network and hardware acceleration technology, which is applied in the data processing field of convolutional neural network hardware acceleration, can solve the problems of slow convolution calculation speed, limited network processing speed, and floating-point data occupying hardware platform storage resources, etc.

Active Publication Date: 2018-11-13
CHONGQING UNIV
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Problems solved by technology

[0006] 1: The input and output of each layer of the Tiny-yolo convolutional neural network and the network weight are all floating-point data. During convolution calculation, data caching and data transmission, floating-point data will occupy a large amount of storage resources on the hardware platform.
[0007] 2: The Tiny-yolo convolutional neural network uses a single-channel input method, and the data of each channel is input one by one, which greatly limits the processing speed of the network
[0008] 3: The convolution calculation of the Tiny-yolo convolutional neural network is performed serially. This calculation method leads to a very slow convolution calculation speed and reduces the processing speed of the network.
[0009] 4: During the detection process of the Tiny-yolo convolutional neural network, the pooling operation needs to be performed after the convolution operation is completed, and there is a large data transmission overhead between the two

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  • Data processing method for hardware acceleration of convolutional neural network
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  • Data processing method for hardware acceleration of convolutional neural network

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[0055] The present invention analyzes the Tiny-yolo network as an example. The present invention analyzes the parallel characteristics of the Tiny-yolo network and combines the parallel processing capability of the hardware (ZedBoard) to analyze Tiny from three aspects: input mode, convolution calculation, and pooling embedding. -yolo convolutional neural network for hardware acceleration. Use the HLS tool to design the corresponding IP core on the FPGA to implement the acceleration algorithm, and realize the acceleration of the Tiny-yolo convolutional neural network based on the FPGA+ARM dual-architecture ZedBorad test.

[0056] see Figure 1 to Figure 6 , a data processing method for hardware acceleration of convolutional neural networks, including embedding pooling operations in convolutional layers. Preferably, it also includes adopting multi-channel parallel input to the convolutional layer. Preferably, it also includes parallel computing of the convolutional layer. Pr...

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Abstract

The invention discloses a data processing method for hardware acceleration of a convolutional neural network. By analyzing the parallel characteristics of the convolutional neural network, and in combination with the parallel processing capability of hardware, the hardware acceleration is carried out on the convolutional neural network. The acceleration scheme is used for performing acceleration improvement on the Tiny-yolo network from three aspects that (1) the processing speed of the Tiny-yolo network is increased through multi-channel parallel input; (2) the convolution computing speed ofthe Tiny-yolo network is increased through parallel computing; and (3) the pooling process time of the Tiny-yolo network is shortened through pooling embedding. The method greatly increases the detection speed of the convolutional neural network.

Description

technical field [0001] The invention relates to the technical field of convolutional neural network hardware acceleration, in particular to a data processing method for convolutional neural network hardware acceleration. Background technique [0002] Convolution Neural Network (CNN) is widely used in the field of computer vision, especially in object detection and image recognition, showing good application prospects. Edge computing is a brand-new computing model whose concept is to process data directly at the edge near the data center without sending it back to the server for processing. The use of edge computing in target detection can bring a series of benefits: directly process the image on the hardware device at the acquisition end without sending it back to the host computer, saving data transmission time and reducing data transmission overhead. It is of great practical significance to realize efficient processing on hardware devices by optimizing and accelerating co...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04
CPCG06N3/045
Inventor 黄智勇李渊明吴海华虞智
Owner CHONGQING UNIV
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