A motherboard and motherboard system based on differential pth vias

Abstract

The invention discloses a motherboard and a motherboard system based on differential PTH vias, including N groups of first differential PTH vias, and the anti_pads of the two first differential PTH vias in each group of first differential PTH vias are independent of each other. And the ratio of the area of ​​the anti_pad of each first differential PTH via to the area of ​​the first differential PTH via is greater than 2 / 3. This method greatly reduces or even avoids that the differential trace has no trace length of the adjacent reference layer due to the excessive sum of the anti_pad areas of the two first differential PTH via holes, resulting in high impedance of the differential trace In addition, by increasing the size of the anti_pad to reduce the parasitic capacitance value, the impedance of the joint between the PTH connector and the main board is reduced, and the signal transmission quality at the joint between the PTH connector and the main board is optimized.

Description

technical field [0001] The invention relates to the technical field of motherboard design, in particular to a motherboard and a motherboard system based on differential PTH vias. Background technique [0002] In the motherboard system design, in order to expand more high-speed IO ((Input / Output, input / output) interface functions, usually when designing the motherboard, it is necessary to develop many subsidiary high-speed IO interconnect daughter boards in parallel. The high-speed IO signal on the motherboard Most of the lines are PCIE lines, which are usually transferred externally (for example, to interconnect daughter boards) through SMT (Surface Mount Technology, surface mount technology) connectors or PTH (Platating Through Hole, through-hole in-line components) connectors. However, since the cost of the SMT connector is higher than that of the PTH connector, the motherboard usually uses the PTH connector for external connection. [0003] The high-speed IO signal lines...

AI Technical Summary

Problems solved by technology

Because the structural size of the differential PTH vias is large, when the differential PTH vias are connected to the PTH connector, a large parasitic capacitance characteristic will be generated at the joint between the PTH connector and the main board, causing the transmission characteristic impedance of the joint to be biased. There are many low target values ​​(see figure 2 ), which makes the signal reflection at this place too large, which affects the signal transmission quality

[0004] In order to optimize the impedance quality of the connection between the PTH connector and the main board, in the prior art, the anti_pad of each group of differential PTH via holes on the main board is dug and merged to form a complete ellipse, which surrounds the Two differential PTH vias, please refer to figure 2 , since the structure of the differential PTH via itself is relatively large, the combined anti_pad is even larger. Although the impedance quality at the connection between the PTH connector and the differential PTH via has a better optimization effect, when the differential PTH via Differential traces connected to differential PTH vias when connected to differential traces (refer to image 3 ) or even other differential traces intersecting this connection area (see Figure 4 ) There is a problem that there is no adjacent reference plane locally, which makes the impedance value of this segment of differential traces too large (please refer to Figure 5 ), which in turn makes the differential line have a large reflection on the signal, which affects the signal transmission quality

It can be seen that on the issue of improving signal transmission quality, the design of differential PTH vias in the prior art cannot achieve compatibility between PTH connectors and differential wiring.

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