50results about How to "Reduce the value of parasitic capacitance" patented technology

The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated.

The invention discloses a capacitance sensor, comprising a sensor gauge head, inner electrodes and an outer electrode, wherein the inner electrode is composed of a plurality of independent electrodes; the inner electrodes are the same in inner and outer diameters and are coaxially arrayed; the inner electrodes respectively comprise a top compensation electrode, a multi-section measurement electrode and a bottom compensation electrode from top to bottom; each two sections of electrodes are connected through a connecting piece which is made of an insulating material; the outer electrode is sleeved at the outer parts of the inner electrodes through screw threads, is coaxially mounted with the inner electrodes and is commonly shared by each section of the electrode in the inner electrodes; and the sensor gauge head is connected with the outer electrode. According to the capacitance sensor disclosed by the invention, the influences on liquid level measurement of temperature, pressure, mediums and the like are eliminated and the precision of the liquid level measurement is improved; and furthermore, an electricity leakage phenomenon can be effectively avoided and the linearity of the sensor is guaranteed.

The invention provides an on-chip integrated inductor, comprising inductive coil, metal layer, isolation layer; A metal layer is provide between two adjacent inductive coils; An isolation layer is arranged between the inductive coil and the metal layer; Looking the adjacent two inductive coils in a down direction, The two coils are offset to each other and not superposed; The inductive coil and the metal layer are connected through perforations. The invention provided on-chip inductors reduces parasitic capacitance between perforation wires, Which improving quality factors, And expanding frequency bandwidth of inductance, Without increasing the chip area.

A display device including a display panel configured to display an image, a touch sensing layer disposed above the display panel and the touch sensing layer including a touch substrate, a touch electrode disposed on the touch substrate, and a common touch electrode disposed under the touch substrate, a first driver configured to apply a sensing input voltage having a first phase to the touch electrode, and a second driver configured to apply a common input voltage having a second phase to the common touch electrode. The second phase of the common input voltage is different from the first phase the sensing input voltage.

A contact pad belongs to protection circuit design field of semiconductor integrated circuit. The contact pad provided by the present invention comprises a pad metal layer, and further comprises a totally depleted layer area formed by simultaneously neutralizing and doping a first type trap and a second type trap for an active region; the totally depleted layer area is located under the pad metal layer and formed at an upper surface layer of a semiconductor substrate. Compared with the prior art, the totally depleted layer area increases a distance between an upper electrode and a lower electrode of the parasitic capacitance of the contact pad, reduces the value of the parasitic capacitance; simultaneously, the preparation of the totally depleted layer area can use the ion implantation of existing art, wherein the operation is simple and extra processes are not needed.

The present invention relates to the field of magnetoelectric technology, in particular to a ring-shaped differential-mode inductor and a production method thereof. The ring-shaped differential-mode inductor includes a ring-shaped magnetic core and a coil, and the ring-shaped magnetic core is connected by a first magnetic core and a second magnetic core. In combination, the window in the middle of each turn coil forms a magnetic core channel, and the first and second magnetic cores are inserted into the magnetic core channel and then docked. The production method of the annular differential mode inductor comprises the following steps: winding the coil by a winding machine, respectively passing the first and second magnetic cores through the coil, while the second magnetic core is passed through the other end of the coil core channel, and the The starting and tail wires are stripped and soldered. In the present invention, the coil passes through the magnetic core after being wound by a winding machine. The winding process is simple, which solves the problem that the wire diameter is too large and cannot be wound. At the same time, it reduces the labor intensity of workers and improves production efficiency; The copper wire will be damaged or have pinholes during the process, which improves the yield.

The invention discloses a microcomputer voltage electric ultrasonic transducer with an etching hole and a sectioned upper electrode. The transducer is provided with a substrate, a structural layer, abottom electrode, a piezoelectric layer and the upper electrode. A working principle of the transducer is that direct and inverse piezoelectric effects are used for realizing conversion from mechanical energy to electric energy or the electric energy to the mechanical energy. The transducer is capable of dividing the upper electrode and the piezoelectric layer in an original square ring structureto four pieces of equal area rectangular structures. Such structure is capable of reducing an opposite area of the upper electrode and the bottom electrode, thereby reducing a stray capacitance, and improving a signal to noise ratio of the ultrasonic transducer. At the same time, small holes are etched at four empty corners, so rigidity of a vibrating diaphragm is advantageously reduced, and transmitting sensitivity of the transducer is improved, thereby loss of the transmitting sensitivity of the transducer caused by reducing the area of the upper electrode is remedied.

The present invention provides a semiconductor transistor structure and a preparation method thereof. The structure comprises: a semiconductor substrate; a grid module located on the semiconductor substrate, wherein the grid module comprises a grid dielectric layer and a grid conductive layer located on the grid dielectric layer; a side wall isolation structure located at the side wall of the gridmodule, wherein the side wall of the grid module comprises a first isolation layer, an air insulation layer and a second isolation layer arranged in order from inside to outside; and bolt conductivelayers located at two sides of the grid module, wherein the side wall isolation structure is configured to separate the bolt conductive layers from the grid module. The semiconductor transistor structure and the preparation method thereof can effectively reduce the stray capacitance value so as to improve the resistance-capacitance delay increasing speed and reduce the switching energy.

The present disclosure provides a semiconductor structure and a manufacturing method for the semiconductor structure. The semiconductor structure manufactured according to the manufacturing method provided in the present disclosure comprises a substrate and a gate formed on the substrate, and a silicon epitaxial layer is formed on the substrate at two sides of the gate; and a side surface of the gate is provided with a first side wall, with a gap being provided between the first side wall and the silicon epitaxial layer, and a surface of the first side wall further comprises a second side wall, with the second side wall covering the gap, so that there is an air gap between the first side wall and the silicon epitaxial layer.

A semiconductor structure and a forming method thereof are provided. The forming method involves a first dielectric layer, a metallide and a second dielectric layer. The first dielectric layer is located on a substrate, covers the side walls of a gate, and has first grooves. The first grooves extend from the first dielectric layer of device regions to the first dielectric layer of isolation regions, and the top and side wall surfaces of source-drain doping layers are exposed at the bottoms of the first grooves. The metallide is located on the surfaces of the source-drain doping layers exposedat the bottoms of the first grooves. The second dielectric layer is located in the grooves of the isolation regions, and exposes the metallide on the top surfaces of the source-drain doping layers. The second dielectric layer can reduce the projection pattern area of the electrical connection structure of the isolation regions on the side wall surface of the gate, so as to reduce the value of parasitic capacitance formed by the electrical connection structure, the gate and the first dielectric layer between the electrical connection structure and the gate and improve the performance of the formed semiconductor structure.