50results about How to "Reduce the value of parasitic capacitance" patented technology

The invention provides a transistor and a forming method of the transistor. The forming method of the transistor comprises the steps that a semiconductor substrate is provided, wherein an isolation structure is arranged in the semiconductor substrate, gate structures are arranged on the surfaces of the portions, on the two sides of the isolation structure, of the semiconductor substrate, and each gate structure comprises a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode located on the surface of the gate dielectric layer; first side walls are formed on the two sides of the gate structure, wherein the first side walls are doped silicon nitride layers; second side walls are formed on the surfaces of the first side walls, and the etching rate of each second side wall is larger than the etching rate of each first side wall; a source electrode and a drain electrode are formed in the portions, located on the two sides of the gate structures, of the semiconductor substrate; metal silicide layers are formed on the surface of the source electrode and on the surface of the drain electrode; the second side walls are eliminated; a stress layer is formed on the surface of the semiconductor substrate. By the adoption of the forming method of the transistor, the stray capacitance on the two sides of the gate structures of the transistor can be reduced, and the stress borne by the trench area of the transistor is increased.

In a capacitance type semiconductor dynamic quantity sensor, a sensor chip and a circuit are connected to each other through adhesive film having an elasticity of 200 MPa or less to reduce the temperature characteristic. Four bonding wires for connecting the sensor chip and the circuit chip are arranged so that each of the bonding wires is located at the center portion of each side portion of the sensor chip or at each corner portion of the sensor chip, thereby sufficiently increasing the interval between the bonding wires and thus sufficiently reducing the absolute value of the parasitic capacitance thus occurring. Therefore, even when the parasitic capacitance between the four bonding wires is varied, the variation is very small, and thus the influence on the sensor characteristic can be reduced.

The invention discloses a bonding welding disk lowering parasitic capacitance and a preparing method thereof, belonging to the technical field of manufacturing semiconductors. The bonding welding disk provided by the invention comprises a welding disk metal layer, a fist semiconductor doping well region, a second semiconductor doping zone and a first semiconductor high-doping zone, wherein, the fist semiconductor doping well region is formed by doping the semiconductor, the second semiconductor doping zone is formed in the fist semiconductor doping well region, and the first semiconductor high-doping zone is formed on the upper surface layer of the second semiconductor doping zone; junction capacitance formed between the first semiconductor doping well region and the second semiconductor doping zone, the junction capacitance formed between the second semiconductor doping zone and the first semiconductor high-doping zone and the junction capacitance formed between the first semiconductor doping well region and the semiconductor substrate are connected in series to lower the equivalent parasitic capacitance value of the bonding welding disk; meanwhile, the second semiconductor doping zone has simple preparing method and increases little cost of the preparing technology of the bonding welding disk.

A semiconductor structure and a fabricating method of the same are provided. The semiconductor structure includes a substate; a first low dielectric constant dielectric layer covering the substate and having a first area and a second area; a plurality of conductive member in the low dielectric constant dielectric layer; an upper lid layer positioned on at least a part of the conductive member; and a dielectric upper lid layer covering the second area of the first low dielectric constant dielectric layer and not covering the first area, wherein the conductive member positioned in the second area has a wider space than the conductive member positioned in the first area. The dielectric upper lid layer preferably has an invariable compressing stress.

The invention relates to a layout structure for shift buffer circuits, which comprises a first shift buffer and a second shift buffer arranged adjacent to the first shift buffer. A first signal and a second signal are received by the first shift buffer and the second shift buffer. The second signal and the first signal are reversed phases to each other. In addition, the first shift buffer and the second shift buffer share the signal line so as to receive the first signal. The shared signal line extends between the first shift buffer and the second shift buffer.