Semiconductor structure and manufacture method thereof

Abstract

A semiconductor structure and a fabricating method of the same are provided. The semiconductor structure includes a substate; a first low dielectric constant dielectric layer covering the substate and having a first area and a second area; a plurality of conductive member in the low dielectric constant dielectric layer; an upper lid layer positioned on at least a part of the conductive member; and a dielectric upper lid layer covering the second area of the first low dielectric constant dielectric layer and not covering the first area, wherein the conductive member positioned in the second area has a wider space than the conductive member positioned in the first area. The dielectric upper lid layer preferably has an invariable compressing stress.

Description

technical field [0001] The invention relates to an interconnection structure of an integrated circuit, and in particular to a damascene process. Background technique [0002] In general, an integrated circuit includes a plurality of metal line patterns separated by spacers of interconnect lines, and interconnect lines such as bus lines, bit lines, word lines, and logic interconnect lines. (logic interconnect lines) multiple inline circuit. These vertically separated patterns of metal lines are electrically connected by vias formed therebetween. Metal lines are formed within trench-like openings and generally extend generally parallel to the semiconductor substrate. According to different circuit technologies, the above-mentioned semiconductor device may include eight or more layers of metal circuits, so as to meet the requirements of device appearance and miniaturization. [0003] One of the existing methods of forming metal lines or vias is the so-called damascene. In g...

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Problems solved by technology

Formed semiconductor structure is fragile due to lack of etch stop layer

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