On-chip integrated inductor

A technology of integrating inductance and inductance coil, which is applied in the field of microelectronics, can solve the problems of large parasitic capacitance, reduce the quality factor Q of inductance and frequency bandwidth, etc., and achieve the effect of reducing parasitic capacitance, improving quality factor and expanding frequency bandwidth

Inactive Publication Date: 2011-08-31
EAST CHINA NORMAL UNIVERSITY +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the traditional stacked inductor structure, the lower inductor coil is located directly below the upper coil, which

Method used

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  • On-chip integrated inductor

Examples

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Embodiment 1

[0023] Such as figure 1 As shown, the on-chip integrated inductor of this embodiment has a one-to-eight-layer structure from bottom to top. The metal layers 1, 3, 5, and 7 are respectively arranged on the first, third, fifth, and seventh layers, and the inductance coils 2, 4, 6, and 8 are respectively arranged on the second, fourth, sixth, and eighth layers. An isolation layer 9 is provided between the two layers to realize electrical isolation between the upper and lower layers.

[0024] figure 2 for use figure 1 The structure diagram of the on-chip integrated inductor realized by the schematic diagram of the standard integrated circuit interconnection shown. figure 2 Among them, a layer of metal layers 3, 5, 7 and isolation layers 12, 13, 14 are arranged between two adjacent layers of inductance coils 2, 4, 6, 8. The inductance coils 2, 4, 6, 8 are connected to the metal layers 3, 5, 7 through the through holes a, b, c, d, e, f.

[0025] Wherein, the areas of the meta...

Embodiment 2

[0034] Figure 6 It is a cross-sectional view of the on-chip integrated inductor in this embodiment. In this embodiment, two metal layers are arranged between two adjacent layers of inductance coils, and the inductance coils 102, 105, 108 are located on the second layer, the fifth layer and the eighth layer. The inductance coil 108 is connected to the metal layer 107 through the perforation f, the metal layer 107 is connected to the metal layer 106 through the perforation e, the metal layer 106 is connected to the inductance coil 105 through the perforation d, the inductance coil 105 is connected to the metal layer 104 through the perforation c, and the metal layer 104 is connected to the metal layer 103 through the through hole b, and the metal layer 103 is connected to the inductance coil 102 through the through hole a. 16 to 28 are isolation layers, and 15 is a substrate.

[0035] Figure 7 It is a top view of the on-chip integrated inductor in this example, the inductan...

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Abstract

The invention provides an on-chip integrated inductor, comprising inductive coil, metal layer, isolation layer; A metal layer is provide between two adjacent inductive coils; An isolation layer is arranged between the inductive coil and the metal layer; Looking the adjacent two inductive coils in a down direction, The two coils are offset to each other and not superposed; The inductive coil and the metal layer are connected through perforations. The invention provided on-chip inductors reduces parasitic capacitance between perforation wires, Which improving quality factors, And expanding frequency bandwidth of inductance, Without increasing the chip area.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to an on-chip integrated inductor. Background technique [0002] At present, integrated circuits tend to develop in the direction of high frequency and low power consumption. On-chip integrated inductors are widely used in circuits such as voltage-controlled oscillators, low-noise amplifiers, and mixers. The performance of the on-chip integrated inductor plays a key role in the circuit. The performance parameters of integrated inductors mainly include quality factor and frequency bandwidth, and the quality factor and frequency bandwidth of the inductor play a decisive factor in improving the performance of the circuit. [0003] Substrate loss, metal coil parasitic resistance, and coil parasitic capacitance all reduce the quality factor and frequency bandwidth of the integrated inductor. The reason for the substrate loss is that the substrate impedance is low,...

Claims

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Application Information

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IPC IPC(8): H01L23/522H01F17/00
Inventor 李小进祝文韬石艳玲王勇蔡静叶红波胡少坚
Owner EAST CHINA NORMAL UNIVERSITY
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