Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure manufactured with the manufacturing method comprises a substrate and a grid formed on the substrate, and silicon epitaxy layers are formed at the portions, located on the substrate, of the two sides of the grid; first side walls are arranged on the side surfaces of the grid, intervals are formed between the first side walls and the silicon epitaxy layers, the surfaces of the first side walls also comprise second side walls, the second side walls cover the intervals, and air gaps areformed between the first side walls and the silicon epitaxy layers. According to the semiconductor structure and the manufacturing method thereof, the dielectric constant of the grid side walls is reduced, stray capacitance of a device is effectively reduced accordingly, and corresponding resistance-capacitance delay time is shortened.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to the field of silicon-on-insulator semiconductors. Background technique [0002] Since the early days when Dr. Jack Kilby of Texas Instruments invented the integrated circuit, scientists and engineers have made numerous inventions and improvements in semiconductor devices and processes. Over the past 50 years, there has been a significant reduction in the size of semiconductors, which translates into ever-increasing processing speeds and ever-decreasing power consumption. So far, the development of semiconductors has roughly followed Moore's Law, which roughly states that the number of transistors in a dense integrated circuit doubles about every two years. Now, the semiconductor process is developing below 20nm, and some companies are working on the 14nm process. Here is just a reference, a silicon atom is about 0.2nm, which means that the distance between two independent componen...

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Problems solved by technology

[0012] In terms of reducing parasitic capacitance, due to technological limitations, it is currently difficult to reduce the value of parasitic capacitance by means of geometric changes

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