Rapid fault tolerance method of normally open faults of nanometer CMOS circuit

A defect and nano technology, applied in the field of nano-CMOS circuit fault-tolerant mapping, can solve the problems of low mapping success rate, poor solution quality, slow mapping method speed, etc., and achieve the effect of reducing the mapping area, eliminating the influence and simplifying the difficulty.

Active Publication Date: 2018-12-07
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is to provide a nano-CMOS circuit under the constraints of connected domains and defects of the nano-CMOS c

Method used

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  • Rapid fault tolerance method of normally open faults of nanometer CMOS circuit
  • Rapid fault tolerance method of normally open faults of nanometer CMOS circuit
  • Rapid fault tolerance method of normally open faults of nanometer CMOS circuit

Examples

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Embodiment 1

[0042] Embodiment 1: Take the simple circuit of three inputs and two outputs shown in Fig. 2 (a) as an example to carry out layering, and its fault-tolerant mapping layered schematic diagram on the defective nanometer CMOS circuit is shown in Figure 4 , 3 input terminals and 3 nodes are respectively mapped on the unit A-E unit, in which the nanodiode 1 between unit BD has a normally-on defect, the output nanowire of unit C is broken at 2, and the bottom CMOS unit of unit E is at 3 There is an unavailable normally open defect. Figure 4 The fast fault-tolerant method for the shown nanometer CMOS circuit includes the following steps:

[0043] Step ①: According to formula (1), calculate the total number of effective defects in the nano-CMOS circuit n def =5; Calculate y (0)=2, y (1)=2, y (2)=1 according to the defect distribution function of formula (2); From the boundary first unit of nanometer CMOS circuit, check unit C, successively B. The CMOS stack defects of A. After ins...

Embodiment 2

[0051] Embodiment 2: with Figure 5 The nano-CMOS circuit structure with a size of 5×4 is shown as an example, and the schematic diagram of the normally-on defect of the nano-diode is shown in Figure 5 .

[0052] Figure 5 The nano-CMOS circuit structure shown includes 20 nano-CMOS units, and the input nanowire of unit F can receive the output signals of unit A and unit B through programmable nano-diodes, and the The logic function; the input nanowire of unit F' can receive the output signal of unit C and unit D, and complete the logic function from Figure 5 It can be seen that the programmable nanodiode located at the intersection of the output nanowire of B and the input nanowire of F is normally on ( Figure 5 Indicated by the square 1 in the center), the programmable nanodiode located at the intersection of the output nanowire of D and the input nanowire of F' is normally open ( Figure 5 Indicated by square 2 in the middle), the actual logical function that can b...

Embodiment 3

[0058] Embodiment 3: with Image 6 The nano-CMOS circuit structure of 8×8 size is shown as an example, and the schematic diagram of its nano-diode normally-on defect is shown in Image 6 .

[0059] When the output nanowire of unit A breaks at point a, the nanodiodes connected to the nanowire at point a and the nanometer CMOS circuit units connected to these nanodiodes cannot receive the output signal of unit A. For unit A, the range of the output connected domain of A is narrowed, and the basic function of the nano-CMOS circuit unit connected below point a remains unchanged, but the total number of units in the input connected domain is reduced by one unit A. Therefore, as long as the associated nodes avoid mapping nano-CMOS cells with broken nanowires and connected nano-CMOS cells beyond the broken point, the defective cells can continue to be used.

[0060] Image 6 The fast fault-tolerant method for the normally-on defect of the shown nanometer CMOS circuit comprises the...

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Abstract

The invention discloses a rapid fault tolerance method of normally open faults of a nanometer CMOS circuit. By use of connected domain modification of a nanometer CMOS unit, possibly normally open fault units are marked and removed from respective connected domains and are continuously used in connection with other units rather than being abandoned. By properly using the fault units, the utilization rate of the unit is improved and mapping area is reduced. Meanwhile, the nanometer CMOS circuit is divided into multiple quite small scales of arrays to carry out local fault tolerance, so the difficulty in fault tolerance is simplified. By combining local optimization results, by use of a taboo searching algorithm and combining an escaping rule, the provided method is verified, so speed of elimination of the normally open faults is increased, the quality of fault tolerance mapping are improved, and the practicability processes of the structure of the nanometer CMOS circuit is accelerated.According to the invention, under the condition that by improving the unit utilization rate and the mapping success rate, effects of logic functions of the nanometer CMOS circuit imposed by the normally open can be rapidly eliminated, and a problem of fault tolerance mapping of the nanometer CMOS circuit is effectively solved.

Description

technical field [0001] The invention relates to a nanometer CMOS circuit fault-tolerant mapping method, in particular to a fast fault-tolerant method for normally open defects of the nanometer CMOS circuit applied in the field of integrated circuits. Background technique [0002] With the continuous shrinking of the line width of the manufacturing process, traditional silicon-based CMOS integrated circuits are rapidly approaching the physical limit of the device, and the increase in manufacturing costs and microscopic quantum effects make it difficult for traditional technologies to meet the needs of current development. With the rapid development of nanoelectronics in recent years, people hope that emerging nanoelectronic devices and corresponding nanocircuits will continue the development of integrated circuits, so that circuits have higher integration density and operating frequency. [0003] In 2005, Likharev and his colleagues proposed the CMOS / nanowire / molecular hybrid...

Claims

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Application Information

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IPC IPC(8): H03K19/20H03K19/0948G11C29/12
CPCG11C29/12G11C2029/1208H03K19/0948H03K19/20
Inventor 夏银水查晓婧储著飞
Owner NINGBO UNIV
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