Method and structure for finfet devices

Abstract

A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer havingnet fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheetdensity, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of thefin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin. Embodiments ofthe invention relate to a method and structure for FinFET devices.

Description

technical field [0001] Embodiments of the invention relate to methods and structures for FinFET devices. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generation after generation of ICs, where each generation of ICs has smaller and more complex circuits than the previous generation of ICs. In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down process also increases the complexity of handling and manufacturing the IC. [0003] For example, field effect transistors (FETs) such as fin field effect transistors (...

AI Technical Summary

Problems solved by technology

Thermal treatment in subsequent process steps can lead to diffusion of implanted dopant impurities

These methods inevitably introduce dopant impurities throughout the fin, detrimentally reducing its carrier mobility

In addition, dopant impurity implantation may also adversely affect the channel strain of the fin

Thus, while conventional penetration mitigation methods are generally adequate for their intended purposes, they are not yet fully satisfactory in all respects

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