Wafer structure and wafer processing method
A processing method and wafer technology, applied in the direction of microstructure technology, microstructure devices, manufacturing microstructure devices, etc., can solve the problems of wafer stress release, wafer deformation, transmission and testing obstacles, etc., to improve yield, damage reduction effect
Active Publication Date: 2020-11-17
无锡感芯科技有限公司
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
When etching and opening holes, it will also generate a lot of heat, and the release of the structure will also lead to the release of wafer stress, wafer deformation, and obstacles to subsequent transmission and testing. The problems are also similar to silicon microphones.
Method used
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[0038] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown.
[0039] It should be understood that when describing a certain structure, when a layer or an area is referred to as being "on" or "over" another layer or another area, it may mean directly on another layer or another area, or Other layers or regions are also included between it and another layer or another region. And, if the structure is turned over, the layer, one region, would be "under" or "beneath" the other layer, another region. If it is to describe the situation directly on another layer or another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein.
[0040]In the description of the...
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Abstract
Disclosed are a wafer structure for forming a plurality of dies and a wafer processing method, wherein the wafer structure comprises a semiconductor substrate; a plurality of functional layers on thesemiconductor substrate, the plurality of functional layers being separated by scribe tracks; a plurality of first grooves located below each of the functional layers; and at least one second groove located around each of the first grooves for balancing stress released by the first groove and storing other substances required during die fabrication. The wafer structure adopts a second groove to balance the stress generated by the first groove, and the second groove can store glue in the packaging process of the chip, thereby facilitating packaging, and can also contain tiny foreign objects generated in the wafer fabrication process, thereby preventing damage to the functional layer of the chip, thereby protecting the wafer structure and the production equipment.
Description
technical field [0001] The present invention relates to the field of semiconductor processing, and more specifically, to a wafer structure and a wafer processing method. Background technique [0002] The manufacturing process of semiconductor integrated circuits can be roughly divided into wafer manufacturing, testing, dicing, and packaging. Wafer is a wafer used to make silicon semiconductor integrated circuits, and its shape is usually circular. The size of the wafer is, for example, 6 inches, 8 inches or 12 inches. A functional layer consisting of a laminated insulating film and a functional film is formed on a wafer, and a plurality of dies arranged in an array are formed using the functional layer. Then, conduct an electrical test on the dies of the wafer, cut the qualified dies from the wafer into independent dies, and then carry out the packaging process such as packaging and bonding of the qualified dies. [0003] Micro-Electro-Mechanical (MEMS, Micro-Electro-Mech...
Claims
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IPC IPC(8): B81B7/02B81C1/00
CPCB81B7/02B81C1/00865
Inventor 万蔡辛
Owner 无锡感芯科技有限公司