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Wafer and chip

A wafer and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve problems such as optical alignment failure, wafer slide damage, wafer warpage deformation, etc., to reduce wafer warpage and improve Wafer yield, the effect of achieving stress balance

Active Publication Date: 2018-12-21
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the manufacturing process of 3D NAND devices is based on a stacked structure, so it is very important to control the stress of the entire wafer, otherwise it is easy to cause warping and deformation of the wafer. Insufficient suction of the Chuck leads to damage or even cracking of the slide. On the other hand, it may lead to failure of optical alignment (Alignment and Overlay), resulting in poor wafer yield

Method used

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Experimental program
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Effect test

Embodiment 1

[0061] In this embodiment, from the level of the wafer, by setting the gate line gaps in different directions in different regions of the wafer, the stress balance is realized and the defect of wafer warping during the wafer manufacturing process is reduced.

[0062] refer to Figure 1-Figure 3 As shown, among them, figure 1 is the exposure field map (shot map) of the wafer, figure 2 and image 3 It is a schematic top view of an exposure field area (shot). The wafer 1 of this embodiment includes a plurality of sub-regions 1a, 1b, and 1c, and a plurality of exposure field areas 10 are arranged in an array in each of the sub-regions 1a, 1b, and 1c. A plurality of chip areas 100 are arranged in an array in each exposure field area 10, and the exposure field area 10 is an area exposed by photolithography once in the wafer manufacturing process.

[0063] refer to Figure 4-6 As shown, the storage area of ​​the chip area 100 includes: a stacked layer 102 located on a substrate ...

Embodiment 2

[0074] In this embodiment, from the level of the effective chip unit, by setting gate line gaps in different directions in different regions, stress balance is achieved, and the defect of wafer warpage in the wafer manufacturing process is reduced.

[0075] It can be understood that, in this application, a chip may exist on a wafer, or may be a bare chip after wafer dicing, or may be a packaged chip.

[0076] Generally, in order to increase the capacity of the chip, multiple planes are usually designed in the storage area of ​​the chip, and each plane has basically the same capacity, that is, has basically the same number of storage units.

[0077] In this embodiment, a chip 100 is proposed, referring to Figure 7 As shown, the storage area of ​​the chip 100 includes a plurality of areas, which are referred to as cell array areas (100a, 100b, 100c, 100d) for ease of understanding and description.

[0078] refer to Figure 7 and Figure 4 , Figure 5 As shown, the cell arra...

Embodiment 3

[0088] In this embodiment, from the plane level of the chip, the gate line gaps in different directions are set in different blocks to achieve stress balance and reduce wafer warpage in the wafer manufacturing process. Defects.

[0089] Generally, in order to increase the capacity of the chip, multiple planes are usually designed in the storage area of ​​the chip, and each plane has basically the same capacity, that is, has basically the same number of storage units. Multiple blocks can be designed in each slice, and each block has basically the same capacity, that is, has basically the same number of storage units.

[0090] In this embodiment, a chip is proposed, refer to Figure 8 As shown, the chip area includes a plurality of block areas, which are referred to as cell array areas (1000a, 1000b, 1000c, 1000d) for ease of understanding and description.

[0091] refer to Figure 8 and Figure 4 , Figure 5 As shown, the cell array region includes: a stacked layer 102 on ...

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Abstract

The invention provides a wafer and a chip, which realize stress balance by arranging gate line slots in different directions in a stack layer. As the gate line gap is formed in the stacked lay and formed in different directions, the stress in the stacked layer can be released in different directions, so that the stress of the wafer or the chip in different directions can be balanced, the defects of the wafer warping in the wafer manufacturing process can be reduced, and the wafer yield can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a wafer and a chip. Background technique [0002] NAND devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. [0003] The planar structure NAND device is close to the limit of actual expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D structure NAND device is proposed. In the 3D NAND device structure, a stack of storage units is vertically stacked to form a string of storage units in the stacked layer, thereby realizing a stacked 3D NAND storage device and improving the integration of the storage device. However, the manufacturing process of 3D NAND devices is based on a stacked structure, so it is very important to control the stress of the entire wafer, otherwise it is easy to cause warping and deformation o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L21/78
CPCH01L21/78H01L27/0203
Inventor 肖莉红李兆松李思晢汤召辉周玉婷
Owner YANGTZE MEMORY TECH CO LTD
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