A NAND Flash solid state storage adaptive error control method

An error control and solid-state storage technology, applied in static memory, instruments, etc., can solve the problems of no general implementation method and no widely recognized standard

Active Publication Date: 2018-12-25
SAGE MICROELECTRONICS CORP
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the application in the field of solid-state storage controllers is still in its infancy, and there is no mature general implementation method, let alone a widely recognized standard.

Method used

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  • A NAND Flash solid state storage adaptive error control method
  • A NAND Flash solid state storage adaptive error control method
  • A NAND Flash solid state storage adaptive error control method

Examples

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Embodiment Construction

[0054] In order to illustrate the specific application of the present invention more clearly, take SLC type NAND Flash as an example;

[0055] A kind of NAND type Flash solid-state storage adaptive error control method, its steps are:

[0056] Step 1: Construct a code check matrix to realize coding;

[0057] The data size of each page is 2048B, and the ECC size is 128B, so the encoding length is 16384b, the parity bit length is 1024b, and the unit matrix is ​​256*256. Let check matrix H=[H 1 h 2 ], where H 1 The specification is 4*256=1024 rows, (64-4)*256=15360 columns, H 2 The specification is 1024 rows and 1024 columns

[0058]

[0059] By calculating the specific left shift digits as follows:

[0060]

[0061] where H 1B The value corresponding to each element in indicates that the corresponding position is replaced by the position in the element after the corresponding position is shifted to the left by the corresponding number of digits. The weight of the ...

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Abstract

A NAND-type flash solid-state storage adaptive error control method includes dividing the data to be stored into groups according to the length of each page of NAND Flash structure before the data isstored in solid state memory, encoding the data according to the constructed encoder, storing the encoded code word in data area according to page, and storing the check bit information in ECC area ofcorresponding page. When reading out data, the data read out by page is decoded by the high-efficiency error-correcting hard data decoding module. If the decoding is successful in a reasonable numberof iterations, the decoding result is output for reading and error-correcting of the next page of data. If the hard data decoding fails or cannot be completed within a reasonable number of iterations, the data recovery soft information decoding is called for data recovery processing at the expense of reducing the timeliness. The invention has the advantages of reliably recovering the high bit error rate data and avoiding the loss of important data.

Description

technical field [0001] The invention belongs to the field of solid-state storage control, and in particular relates to an adaptive error control method for NAND-type Flash solid-state storage. Background technique [0002] Nand Flash is widely used in solid-state hard drives. The change of the threshold voltage of the floating gate in the NAND Flash unit will affect the threshold voltage distribution of adjacent flash memory units due to the existence of parasitic coupling capacitance, resulting in bit flipping. In addition, due to the influence of storage materials and production processes, bad blocks will inevitably be generated during production and use, and radiation in the space environment may also cause single-event flips to cause errors, making the data stored in Nand Flash and read out again inconsistent. In perfect agreement, an error occurs, and the probability of this error increases with the increase in the number of erasing / programming. Therefore, it is necess...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G11C29/44
CPCG11C29/42G11C29/4401
Inventor 王祖良张婷
Owner SAGE MICROELECTRONICS CORP
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