Digital storage oscilloscope with functions of high-speed serial protocol triggering and decoding
A high-speed serial and digital storage technology, applied in digital variable display, digital variable/waveform display, instrument, etc., can solve the problem of increasing hardware cost and achieve the effect of saving hardware cost
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[0024] figure 1 It is a principle diagram of a specific embodiment of the digital oscilloscope with high-speed serial protocol triggering and decoding functions of the present invention.
[0025] In this example, if figure 1 As shown, the present invention has a digital storage oscilloscope with high-speed serial protocol triggering and decoding functions, including signal conditioning channels, analog-to-digital converters, control modules, waveform data storage, microprocessors, and display screens in the prior art. The acquisition, storage, and display of serial protocol signal waveforms are the same as those of ordinary digital oscilloscopes, and will not be repeated here. In order to realize the triggering and decoding functions of the high-speed serial protocol by hardware, an acquisition FPGA array and a processing FPGA are also designed in the present invention.
[0026] Such as figure 1 As shown, for simplicity, figure 1 Only the case of a single serial protocol a...
example
[0064] Taking the realization of the protocol triggering / decoding function of PCI-Express 1.0 as an example, the specific implementation of the present invention will be described in detail below.
[0065] PCIe is a high-speed serial computer expansion bus standard. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices have exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, and end-to-end reliability. Transmission, hot plugging, and quality of service (QOS) functions. Its main advantage is high data transfer rate, the PCI-Express 1.0 signal rate in this embodiment is 2.5Gb / s.
[0066] Table 1 is the TLP frame format;
[0067] STP
ID
TLP Header
Date payload
ECRC
LCRC
END
1Byte
2Bytes
3 / 4DW
0~1024DW
1DW
1DW
1Byte
[0068] Table 1
[0069] The TLP frame of PCI-E follows the frame form...
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