Dynamic comparator offset voltage calibration method

Abstract

The present invention provides a dynamic comparator offset voltage calibration method, belonging to the technical field of a simulation integration circuit. The dynamic comparator offset voltage calibration method is suitable for a successive approximation analog-digital converter in a down plate sampling mode, the digital analog converter of the successive approximation analog-digital converter is internally provided with a calibration capacitance array with the same structure as a quantization capacitor array to achieve calibration for the comparator offset voltage; the quantization processof the digital analog converter of the successive approximation analog-digital converter comprises a calibration mode and a normal working mode, the successive approximation analog-digital converter is used to perform quantization of 0 to obtain offset codewords in the calibration mode, the switching of the capacitor in the calibration capacitor array is controlled according to the offset codewords in the normal working mode to obtain eliminate the output quantization codewords of the comparator offset voltage. The dynamic comparator offset voltage calibration method can eliminate the relatedinfluence of the comparator offset voltage in the output quantization codewords obtained in the successive approximation analog-digital converter, is simple in logic, easy to achieve and high in calibration precision and does not need real-time fresh.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a method for calibrating the offset voltage of a dynamic comparator used for sampling successive approximation analog-to-digital converters (SAR ADC) on a lower plate. Background technique [0002] With the rapid development of mobile communications, portable test instruments, and consumer electronics wireless communications, the higher the speed of the analog-to-digital converter (ADC), the better, and the lower the power consumption, the better. Compared with the traditional high-speed and high-precision pipeline (pipeline) ADC, the successive approximation (SAR) ADC has the characteristics of simple structure, small area, low power consumption, low cost, etc., the continuous reduction of process feature size and the application of some technologies (such as time interleaving, multi-bit shifting, etc.) also make SAR ADC have the possibility to rea...

AI Technical Summary

Problems solved by technology

[0004] Aiming at the problems of small quantization range and performance degradation of the SAR ADC caused by the offset voltage of the comparator in the above-mentioned SAR ADC, as well as the power consumption problem existing in the traditional method of eliminating the offset of the comparator, the present invention proposes a sampling technology applicable to the lower plate The offset voltage calibration method of the successive approximation analog-to-digital converter SAR ADC dynamic comparator, the logic is simple and easy to implement, and the calibration accuracy can reach 1 LSB (ADC minimum resolution)

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