Low dropout linear voltage regulator circuit without external capacitor

Abstract

The invention discloses a low-voltage-difference linear voltage-stabilizing circuit without an external capacitor. The circuit comprises an NMOS transistor, a bypass capacitor, a feedback circuit, a comparison circuit and a charging and discharging circuit, wherein the source of the NMOS transistor serves as the output end of the voltage-stabilizing circuit; the feedback circuit is used for feeding back an output voltage of the voltage-stabilizing circuit to output a first feedback voltage and a second feedback voltage; the comparison circuit is used for comparing the first feedback voltage with a reference voltage to output a first comparison signal, and comparing the second feedback voltage with a reference voltage provided by a reference voltage end to output a second comparison signalthrough a second output end; and the charging and discharging circuit is used for charging and discharging the bypass capacitor according to the first comparison signal and the second comparison signal to adjust a gate driving voltage provided by a first node, thereby enabling the output voltage of the voltage-stabilizing circuit to be kept in a preset voltage interval by controlling the NMOS transistor. According to the voltage-stabilizing circuit, the output fluctuation and the power supply noise can be effectively inhibited, the stability is high, and the response is sensitive.

Description

technical field [0001] The invention relates to the technical field of low-dropout linear voltage stabilization, in particular to a low-dropout linear voltage stabilization circuit without an external capacitor. Background technique [0002] With the reduction of digital logic supply voltage, LDO (Low Dropout Regulator, low dropout linear regulator) is widely integrated in various MCU (Micro-Control Unit, micro control unit), DSP (Digital Signal Processing, digital signal processing), etc. Digital logic chip. [0003] figure 1 It is a structural schematic diagram of a traditional LDO. Such as figure 1 As shown, the LDO relies on the equivalent series resistance ESR of the external capacitor C at the output to compensate a left-half-plane zero point for the system to keep the system stable. This requires application engineers to select an external capacitor C with a specific ESR value range, which will increase the complexity and cost of the application, and this external...

AI Technical Summary

Problems solved by technology

However, in fact, it is impossible to consider all external and internal conditions clearly, and there will inevitably be negligence, which may cause the output ripple of the LDO to increase, or even oscillate

The output ripple of the LDO will directly affect the stability of the digital circuit. If the product requires high stability, these slight negligence will have a fatal impact.

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