Three-dimensional memory structure and manufacturing method thereof

Abstract

Disclosed is a manufacturing method of a three-dimensional memory structure. The manufacturing method includes: forming a CMOS (complementary metal oxide semiconductor) circuit including a first silicon substrate and a first insulating layer arranged on the first silicon substrate, wherein the first insulating layer is provided with a plurality of first outer pads; forming through-silica vias running through the first insulating layer and the first silicon substrate, wherein the first ends of the through-silica vias are electrically connected with the first outer pads, and the second ends of the through-silica vias are exposed from the bottom of the first silicon substrate; forming a storage unit array including a second silicon substrate and a second insulating layer arranged on the second silicon substrate, wherein the second insulating layer is provided with a plurality of second outer pads; bonding the COMS circuit to the storage unit array to form the three-dimensional memory structure, wherein the first silicon substrate of the CMOS circuit is in contact with the second insulating layer of the storage unit array, the through-silica vias are bonded to the second outer pads toelectrically connect the CMOS circuit and the storage unit array. The manufacturing method according to an embodiment of the invention helps improve storage density and reduce wiring density.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a three-dimensional memory structure and a manufacturing method. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the aperture of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, three-dimensionally structured memory devices (ie, three-dimensional memory structures) have been developed. The three-dimensional memory structure includes a plurality of memory cells stacked along the vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] In the three-dimensional memory structure of the NAND structure, one is to form a CMOS circuit first, and then form a memory cell array on...

AI Technical Summary

Problems solved by technology

In this three-dimensional memory structure, the through array contact (Through Array Contact) occupies a large chip area, which makes the area of ​​the core area smaller, thereby reducing the storage density; in addition, a large number of metal wirings are used to provide CMOS circuits and memory cell arrays. The increase in wiring density will affect the yield and reliability of the three-dimensional memory structure

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