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A FPGA resource layout method and device

A layout method and layout technology, applied in geometric CAD, CAD circuit design, instruments, etc., can solve the problems of layout failure, high occupation rate of layout resources, and insufficient utilization of layout resources, etc.

Active Publication Date: 2019-02-22
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is that the resources that can be laid out in the prior art cannot be fully utilized, and the layout fails when the occupancy rate of the layout resources is high

Method used

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  • A FPGA resource layout method and device
  • A FPGA resource layout method and device
  • A FPGA resource layout method and device

Examples

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no. 1 example

[0067] In order to solve the problem in the prior art that layoutable resources cannot be fully utilized and layout fails when the occupancy rate of layout resources is high. This embodiment provides a FPGA resource layout method. The FPGA resource layout method determines the number of currently idle resources based on the current resource usage, wherein the current resource usage is composed of N columns and M rows of two-dimensional coordinates, and each coordinate As a grid resource, N and M are integers and greater than 1, and then obtain the layout information of the group unit to be laid out. The layout information includes the number of grid resources occupied by the group unit to be laid out. When the number of currently idle resources is judged When it is greater than or equal to the number of grid resources occupied by the units of the layout group to be placed, the units of the layout group to be placed are laid out according to the number of idle resources. For de...

no. 2 example

[0111] This embodiment is based on the first embodiment, taking a specific FPGA resource layout method as an example to further illustrate the present invention. For details, please refer to Figure 9 .

[0112] S901: Classify the layout group units to be arranged according to a preset classification rule, and perform layouts for the classified resources respectively.

[0113] In this embodiment, the layout group units to be placed are classified according to resource types, for example, LUT, FF, DRM, DSP, DLL, etc., and then layout is performed on the classified resources respectively. It can be understood that, for the convenience of description, what is introduced here is the layout for a certain resource.

[0114] S902: Determine the number of currently idle resources based on the current resource usage.

[0115] It should be clear that the current resource usage is composed of N columns and M rows of two-dimensional coordinates, each coordinate is used as a grid resourc...

no. 3 example

[0139] This embodiment provides an FPGA resource layout device, please refer to Figure 10 As shown, the FPGA resource layout device provided in this embodiment includes a determination module 1001, an acquisition module 1002, a determination module 1003, and a layout module 1004;

[0140] Wherein, the determination module 1001 in this embodiment is used to determine the number of currently idle resources based on the current resource usage. The current resource usage is composed of two-dimensional coordinates in N columns and M rows, and each coordinate is used as a grid resource. N and M are integers and greater than 1;

[0141] The obtaining module 1002 is used to obtain the information to be laid out of the group unit to be laid out, and the information to be laid out includes the number of grid resources occupied by the group unit to be laid out;

[0142] The judging module 1003 is used to judge whether the number of currently idle resources is greater than or equal to t...

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Abstract

A FPGA resource layout method and device are disclosed. The method determines the number of currently idle resources according to the current resource usage, where the current resource usage consistsof two-dimensional coordinates of N columns and M rows, As a grid resource, N, M are integers and more than 1, thereby obtaining the information to be laid out of the unit to be laid out, the information to be laid out includes the number of grid resources occupied by the unit to be laid out, and when it is judged that the number of currently idle resources is greater than or equal to the number of grid resources occupied by the unit to be laid out, the unit to be laid out is laid out according to the number of idle resources. The present invention solves the problem that the layout resourcescannot be fully utilized and the layout fails when the occupation rate of the layout resources is high in the prior art. The invention also discloses an FPGA resource layout device. By implementing the scheme, the occurrence of layout failure caused by high layout resource occupancy rate is avoided, and the success rate of the FPGA resource layout is greatly improved.

Description

technical field [0001] The present invention relates to the technical field of Field Programmable Gate Array (FPGA), and more specifically, relates to an FPGA resource layout method and device. Background technique [0002] In modern digital circuit design, the circuit design process is becoming more and more complex. Because the FPGA chip has programmable functions, it simplifies the process of digital circuit design. However, as the design scale of digital circuits becomes larger and more resources are available, the performance requirements for FPGA software layout are also getting higher and higher. [0003] FPGA resources are generally divided into three types: configurable logic cell block (CLB), input / output unit (IO) and programmable routing resources. Among them, CLB can be divided into many different units according to the function, such as LUT (look-up table), FF (flip-flop), RAM (random access memory), DSP (digital signal processing module, such as multiplier u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/18G06F30/34
Inventor 刘焦
Owner SHENZHEN PANGO MICROSYST CO LTD