A CPLD/FPGA register control method and system

Abstract

The invention provides a CPLD / FPGA (Complex Programmable Logic Device / Field Programmable Gate Array) register control method. The method comprises the following steps: receiving and registering an abnormal electric state signal through a first register; receiving a normal electric state signal, an abnormal electric state signal from the first register and a fault state flag bit level through the selector; selectively transmitting an abnormal electric state signal or a normal electric state signal to the second register through the selector based on the fault state flag bit level; and the second register registers the received abnormal electric state signal or the normal electric state signal and transmits the abnormal electric state signal or the normal electric state signal to the BMC fordisplay. According to the method, the BMC is ensured to obtain necessary signal information, meanwhile, transmission information is increased, mainboard CPLD / FPGA management information is perfected,and the method has an important reference value for debugging and fault positioning.

Description

technical field [0001] The present invention generally relates to the computer field, and more specifically, relates to a CPLD / FPGA register control method and system. Background technique [0002] In the server system, the power-on and power-on sequence control, LED indication control, communication control, button detection, power-down detection, fan control, hard disk indication control, etc. of the entire server are usually controlled by the CPLD / FPGA chip. Among them, the CPLD / FPGA chip is used to realize Signal monitoring and signal display in cooperation with BMC are important contents of server design. [0003] BMC is an important part of the server system, which is independent of the system hardware and does not depend on the operating system, so it can cooperate with other component systems to manage the platform of the entire system, such as remote diagnosis, console support, configuration management, hardware management and failure exclude. BMC can communicate ...

AI Technical Summary

Problems solved by technology

However, CPLD / FPGA provides a large number of available signals, which means consuming a large amount of logic resources, which is not allowed for principle changes in the molding design stage; at the same time, for products that are still in the early design stage, CPLD / FPGA logic is added to realize BMC comprehensive monitoring Resources therefore bring about an increase in production costs, which is not recommended

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