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A multi-CPU architecture visual compilation and debugging system and method

A debugging system and debugging method technology, applied in compiler construction, visual/graphical programming, creating/generating source code, etc., can solve problems such as poor reliability and low debugging efficiency, achieve simple architecture, facilitate debugging management, and improve compilation. The effect of debugging efficiency

Active Publication Date: 2019-03-12
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Therefore, the present invention provides a visual compilation and debugging system and method of multi-CPU architecture, which overcomes the defects of low efficiency and poor reliability of parallel compilation and debugging of multi-CPU system architecture in the prior art

Method used

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  • A multi-CPU architecture visual compilation and debugging system and method
  • A multi-CPU architecture visual compilation and debugging system and method
  • A multi-CPU architecture visual compilation and debugging system and method

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Embodiment 1

[0027] The embodiment of the present invention provides a visual compilation and debugging system of multi-CPU architecture, which can be applied to the visual compilation of multi-CPU architecture in the DC control and protection system, such as figure 1 As shown, the system includes:

[0028] Visual compiling computer 1, port router 2 and multiple target compiling boards 3, wherein the visual compiling computer 1 receives compiling task parameters input by the user, generates compiling task plans for each target compiling board according to compiling task parameters, and generates compiling task plans according to compiling task plans The compilation task sequence is correspondingly sent to each target compilation board 3 through the port router 2; each target compilation board 3 respectively executes the compilation task according to the compilation task sequence.

[0029] Through the above-mentioned visual compilation and debugging system system of multi-CPU architecture, ...

Embodiment 2

[0040] The embodiment of the present invention also provides a visual compilation and debugging method of multi-CPU architecture, such as Figure 4 As shown, the method includes the following steps:

[0041] Step S1: Obtain compilation task parameters input by the user.

[0042] In the embodiment of the present invention, the library function pointer chain, debugging IP, CPU port information, wherein, the library function pointer chain is used to represent the library function logic link of the compilation task; the debugging IP is used to represent the compilation task according to the compilation task plan. The address information of the target compilation board; the CPU port information is used to characterize the port of the CPU in the target compilation board according to the debugging IP.

[0043] Step S2: Generate a compilation task plan for each target compilation board according to the compilation task parameters.

[0044] In the embodiment of the present invention,...

Embodiment 3

[0052] An embodiment of the present invention provides a computer device, such as Figure 5 As shown, it includes: at least one processor 401 , such as a CPU (Central Processing Unit, central processing unit), at least one communication interface 403 , memory 404 , and at least one communication bus 402 . Wherein, the communication bus 402 is used to realize connection and communication between these components. Wherein, the communication interface 403 may include a display screen (Display) and a keyboard (Keyboard), and the optional communication interface 403 may also include a standard wired interface and a wireless interface. The memory 404 may be a high-speed RAM memory (Ramdom Access Memory, volatile random access memory), or a non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory 404 may also be at least one storage device located away from the aforementioned processor 401 . where processor 401 can execute Figure 4 In th...

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Abstract

The invention discloses a visual compiling and debugging system and method with multi-CPU structure, By receiving the compilation task parameters entered by the user, according to the compilation taskparameters to generate the compilation task plan of each target compilation board, and generates a multi-CPU intelligent compilation task sequence according to the compilation task plan, small temporary LAN architectures are established through port routers, multiple multi-CPU target compiler boards can be compiled and updated in parallel in lab or engineering field, Instead of compiling functions one board at a time, the compilation and debugging efficiency of the multi-CPU architecture control protection system is obviously improved, Save a lot of CPU architecture system debugging time, atthe same time through the multi-CPU architecture goal of automatic and systematic compilation management, through pointer positioning, can achieve the traceability of all compilers, convenient for debuggers to debug and manage a large number of CPUs in the system in parallel.

Description

technical field [0001] The invention relates to the field of network intrusion detection, in particular to a visual compiling and debugging system and method of multi-CPU architecture. Background technique [0002] The control strategy, protection strategy and monitoring node of the converter valve in the existing DC transmission are relatively complicated, so the calculation scale, calculation speed and calculation accuracy of the DC control and protection system are very high on the control strategy, protection strategy and monitoring node . In the design of the DC control and protection system, a large number of micro-CPUs, including FPGAs and DSPs, are used to implement a large number of real-time calculations of strategies. During the CPU strategy change, it is necessary to manually and repeatedly operate the visualization system one by one to compile the update program for each CPU that needs to be modified. When there are dozens or hundreds of CPUs in the DC control ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/34G06F8/30
CPCG06F8/34G06F8/37
Inventor 王华锋林志光吴文祥杨树森杨建伟马浩宇刘近杨兵建
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD