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Trace structure and chip comprising the same

A wire structure and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of large space, unfavorable layout space utilization, improvement, etc., and achieve the effect of reducing the occupied space

Active Publication Date: 2019-03-15
HEFEI ESWIN IC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the space occupied by the existing single-layer wiring is still relatively large, which is not conducive to the improvement of the utilization rate of the layout space

Method used

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  • Trace structure and chip comprising the same
  • Trace structure and chip comprising the same
  • Trace structure and chip comprising the same

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Experimental program
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Embodiment Construction

[0031] As mentioned in the background technology, the space occupied by the existing single-layer wiring is still relatively large, such as figure 1 with figure 2 As shown, the inventor found that the main reason for this problem is that in order to avoid the contact between the lower traces 11 and the through holes 101 of the upper traces 10, the vias 101 are arranged on two adjacent upper traces 10 In between, through the bridge 102 to connect the through hole 101 and its upper trace 10, and then overlap the projection of the lower trace 11 and the upper trace 10 to avoid the contact between the lower trace 11 and the through hole 101, but this causes the upper trace The space occupied by the line 10 and the lower-layer wiring 11 is relatively large.

[0032] Based on this, the present invention provides a wiring structure to overcome the above-mentioned problems in the prior art, including a substrate and a first wiring layer, an insulating layer and a second wiring layer...

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PUM

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Abstract

The invention provides a trace structure and a chip comprising the same. A first trace layer comprises m pieces of first traces; a second trace layer comprises n pieces of second traces which are arranged in parallel; each second trace is provided with a first through hole, and the first through holes penetrate through the first trace layer, an insulation layer and a second trace layer; the projection of each second trace on a substrate covers the projection of each first through hole on the substrate; each first trace comprises a first trace part, a second trace part and a connecting line forthe first trace part and the second trace part; the projection of the first trace part of the ith first trace and the projection of the jth second trace on the substrate are overlapped; the projection of the second trace part of the ith first trace and the projection of the (j+1)th second trace on the substrate are overlapped, or the projection of the second trace part of the ith first trace andthe projection of the (j-1)th second trace on the substrate are overlapped; and the second trace part and the connecting line surround the first through holes but are not in contact with the first through holes so as to reduce space occupied by the first traces and the second traces.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, more specifically, to a wiring structure and a chip with the wiring structure. Background technique [0002] At present, a large number of signal lines of the same nature, such as bus lines (BUS), voltage division selection lines, etc., are often a large number of lines extending in the same direction in the implementation of the chip layout. Since the receiving end circuits electrically connected to the wires are mostly arranged in an array, and the area of ​​the circuit array often depends on the space occupied by the wires, the wires are usually divided into upper and lower layers in the prior art. The area of ​​the circuit array is reduced, and the utilization rate of layout space is improved. However, the space occupied by the existing single-layer wiring is still relatively large, which is not conducive to improving the utilization rate of the layout space. Contents of the in...

Claims

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Application Information

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IPC IPC(8): H01L23/522
CPCH01L23/522H01L23/5226
Inventor 张孝珩
Owner HEFEI ESWIN IC TECH CO LTD