Memory cell structure of SRAM

Abstract

The invention discloses a memory cell structure of an SRAM. The memory cell structure comprises a pair of pull-up transistors, a pair of pull-down transistors, a pair of selection transistors and a pair of auxiliary transistors; the selection transistors and the auxiliary transistors are both formed in a first active region; the pull-up transistors are formed in a second active region; the pull-down transistors are formed in a third active region; the gates of the pull-up transistors extend from the second active region to the first active region, so that the auxiliary transistors can be formed; and the source regions of the auxiliary transistors are connected with auxiliary electrodes, and therefore, the auxiliary transistors can be connected in parallel with the corresponding pull-down transistors during a reading process so as to increase pull-down current, and can be connected in parallel with the corresponding selection transistors during a writing process so as to increase write-in current. Since the widths of the channel regions of the transistors in the same active region are equal, so that the width of the active region can be kept constant, and the gradual change of the width of the active region can be prevented. With the memory cell structure of the SRAM of the invention adopted, the influence of the width change of the active regions on the length and the width ofthe channels of the transistors can be eliminated, and therefore, the degree of matching between devices can be improved, and yield can be improve, and a read / write window can be expanded, and readingand writing speed can be improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a memory unit structure of an SRAM. Background technique [0002] like figure 1 Shown is the layout of the memory cell structure of the existing SRAM; figure 2 Yes figure 1 The circuit diagram of the storage cell structure of the existing SRAM shown, the storage cell structure of the existing SRAM is composed of a first NMOS transistor 101, a second NMOS transistor 102, a first PMOS transistor 103, a second PMOS transistor 104, and a third NMOS transistor 105 The 6 transistors are connected with the fourth NMOS transistor 106, the first PMOS transistor 103 and the second PMOS transistor 104 are used as two pull-up transistors (Pull Up, PU), and the third NMOS transistor 105 and the The fourth NMOS transistor 106 serves as two pull-down transistors (PullDown, PD). figure 1 Among them, the first NMOS transistor 101 is also represented by PG1, the second NMOS transistor 102...

AI Technical Summary

Problems solved by technology

These situations limit the read and write windows of existing structures

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