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Full-digital phase-locked loop

A phase-locked loop, all-digital technology, applied in the direction of electrical components, automatic power control, etc., to achieve the effects of reduced production and success rate, good loop efficiency, and reduced production costs

Inactive Publication Date: 2002-11-27
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, although fully digitized PLLs have many advantages that analog PLLs do not have, they have an important disadvantage: they require a sampling clock that is many times higher than the frequency of the output signal to divide the clock cycle into many parts
The purpose of the invention is to provide a digital phase-locked loop using all-digital technology, but it still has the defect of being affected by external conditions such as temperature, voltage and manufacturing process

Method used

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  • Full-digital phase-locked loop
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Embodiment Construction

[0032] The present invention is described in detail as follows in conjunction with accompanying drawing and embodiment:

[0033] figure 1 It is a block diagram of an embodiment of an all-digital phase-locked loop of the present invention. The fully digital PLL 10 includes five parts: a frequency divider 20 for division by N, a phase-frequency detector 30 , a K-counter 40 , a digitally controlled oscillator 50 and a frequency divider 60 for division by M. Among them, the values ​​of M and N are set different values ​​according to different applications, in principle, the input variation of the phase-frequency detector is minimized. The output signals "UP" and "DN" of the phase difference detector 30 will be determined by the phase difference and frequency difference (ωin-ωout) relationship of the two input signals φin and φout. at the same time as figure 1 Shown, fc represents a local clock, by changing its frequency and phase to lock the input clock fin. figure 1 Lfc / 2 in ...

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Abstract

An all-digital phase-locked loop, including: a, a digitally controlled oscillator; b, a K-counter to provide the first control signal to the digitally controlled oscillator; c, a phase-frequency detector, which receives and compares The output signal of the digitally controlled oscillator is compared with the input signal, and a second control signal is sent to the K-counter according to the comparison result. The digitally controlled oscillator consists of a delay line, an address generator and a multiplexer. The delay line includes flip-flops with a phase difference between each flip-flop. The address generator receives the first control signal generated by the K-counter and generates an address for the multiplexer according to the signal. Wherein, the delay line includes an L-stage shift register to generate L local clocks with different phases, wherein L is an integer.

Description

technical field [0001] The invention relates to a fully digital phase locked loop (phase locked loop, PLL). Especially with regard to an improved fully digital phase-locked loop, which can provide the advantages of low cost, high stability, and extremely narrow bandwidth. Background technique [0002] A phase-locked loop is a circuit used to lock the frequency and phase of an input clock signal. In other words, a phase-locked loop is a circuit used to generate an output signal that is synchronized with the frequency and phase of an input reference clock signal. . The phase-locked loop can also be regarded as a demodulator (demodulator), which is used to demodulate the carrier frequency, that is, to track or synchronize the frequency and phase changes of the input clock. [0003] Phase-locked loops are widely used in many fields, such as communication systems, computer and television engineering, etc. Generally speaking, phase-locked loops can be divided into three categor...

Claims

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Application Information

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IPC IPC(8): H03L7/081H03L7/089H03L7/099H03L7/18
CPCH03L7/089H03L7/0991H03L7/18H03L2207/50
Inventor 王博民
Owner IND TECH RES INST