A DMA transmission method and a DMA controller suitable for network transmission

Abstract

The invention discloses a DMA transmission method suitable for network transmission and a DMA controller. The method comprises the following steps of: selecting a Write DMA; addresses of a storage space reserved at a host side are written into an FIFO memory equipped at a board card side in sequence in advance; the DMA controller of the board card end can autonomously generate a descriptor according to the address stored in the FIFO memory and the transmission data of the board card end; and the descriptor does not need to be maintained at the host side again, so that the number of interactiontimes between the host side and the board card side is reduced, the Write DMA data transmission efficiency is improved, and the workload of the host side is reduced. For Read DMA, the host end actively generates the descriptor instead of regenerating the descriptor after waiting for interruption, so that the board card end does not need to wait for the host end to regenerate the descriptor, the interaction time between the host end and the board card end is reduced, and the Read DMA data transmission efficiency is improved.

Description

technical field [0001] The invention relates to the field of DMA transmission, in particular to a DMA transmission method and a DMA controller suitable for network transmission. Background technique [0002] In the prior art, DMA (Direct Memory Access, direct memory access) transmission under network transmission includes Write DMA and Read DMA. Please refer to figure 1 , figure 1 It is an implementation schematic diagram of a DMA transmission in the prior art. Write DMA refers to the FPGA (Field-Programmable Gate Array, field programmable logic gate array) terminal to transmit data to the host terminal, and Read DMA refers to the host terminal to transmit data to the FPGA terminal. The FPGA side (that is, the board side) is configured with a PCIE (peripheral component interconnect express, peripheral component high-speed interconnection standard) controller, a DMA controller, and a Smart NIC (Network Interface Card, network card). [0003] For Write DMA, after the board...

AI Technical Summary

Problems solved by technology

It can be seen that in DMA transmission, the number of interactions between the host and the board is relatively large, and the board needs to wait for the host to regenerate the descriptor each time, resulting in a long time for the interaction between the two, thereby reducing the DMA transmission efficiency

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