Protection method for a processor instruction Cache single event upset soft error

Abstract

The invention provides a protection method for a processor instruction Cache single event upset soft error, and the method comprises the steps: determining a fault abnormity type caused by the processor instruction Cache single event upset; binding a single particle flipping soft error recovery function according to the fault abnormality type; starting a corresponding single event upset soft errorrecovery function according to the fault abnormality type; through a single event upset soft error recovery function, storing a return address in an abnormal return address register of the processor,and invalidating an instruction Cache of the processor; determining an address where the single event upset occurs by returning the address; and re-acquiring data corresponding to the address where the single event upset occurs from the main memory, and executing data restoration of the single event upset. Therefore, the problem of program soft errors caused by single event upset when the processor is applied to a satellite-borne computer is solved, and the method has the advantages of simple structure, low cost, high execution efficiency and wide applicability.

Description

technical field [0001] The present invention relates to the field of aerospace technology, in particular to a protection method for processor instruction Cache single event flipping soft errors. Background technique [0002] With the development of spacecraft in the direction of long life and high reliability, galactic cosmic rays, solar cosmic rays, and high-energy charged particles in the Earth's radiation belt, especially the single-particle flips caused by heavy ions, have become a must for the reliable operation of spacecraft in orbit. A key factor to focus on. Single event upset is the effect of charged particle radiation on logic devices and logic circuits. When a single space high-energy charged particle bombards the chip of a microelectronic device in a large-scale or ultra-large-scale integrated circuit, it will cause a transient logic error or hard error in the logic device or circuit, such as the flipping of the data stored in the memory cell ("1" flipping to "...

AI Technical Summary

Problems solved by technology

[0004] However, there is no hardened PPC750 processor corresponding to RAD750 in China at present, and the research on radiation resistance hardening of this high-speed processor is just in its infancy

As the main single-event-sensitive component of a high-performance processor, the single-event flip in the instruction cache will cause soft errors in the program flow, which will bring problems to the application of the processor in on-board computer products

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